Semiconductor memory device

A semiconductor memory device comprising:

• a substrate;
• a stacked body provided on the substrate and including a plurality of electrode layers, the electrode layers being stacked apart from each other in a first direction and extending in a second direction parallel to an upper surface of the substrate;
• a plurality of first members provided in the stacked body and extending in the first direction and the second direction,
• at least one first insulating member provided in the stacked body and extending in the first direction and a third direction so that the electrode layers are divided into a plurality of regions in the second direction, the third direction intersecting with the second direction and being parallel to the upper surface of the substrate;
• an interconnect provided between the substrate and the stacked body;
• a plurality of columnar portions provided in the stacked body and extending in the first direction, each of the columnar portions including a semiconductor portion;
• and
• a piercing via piercing the stacked body and connected to the interconnect in a third region provided between a first region in which the columnar portions are located and a second region in which the first insulating member is located.

A semiconductor memory device, comprising:

• a substrate;
• a stacked body provided on the substrate and including a plurality of electrode layers, the electrode layers being stacked apart from each other in a first direction and extending in a second direction parallel to an upper surface of the substrate;
• a plurality of first members provided in the stacked body and extending in the first direction and the second direction;
• at least one first insulating member provided in the stacked body and extending in the first direction and a third direction so that the electrode layers are divided into a plurality of regions in the second direction, the third direction intersecting with the second direction and being parallel to the upper surface of the substrate;
• and
• a supporting member provided between the substrate and the stacked body,
• wherein the first insulating member includes an intersecting portion intersecting with at least one of the first members, and
• the intersecting portion is located on the supporting member.

A semiconductor memory device, comprising:

• a substrate;
• a stacked body provided on the substrate and including a plurality of electrode layers, the electrode layers being stacked apart from each other in a first direction and extending in a second direction parallel to an upper surface of the substrate;
• a plurality of first members provided in the stacked body and extending in the first direction and the second direction;
• at least one first insulating member provided in the stacked body and extending in the first direction and a third direction so that the electrode layers are divided into a plurality of regions in the second direction, the third direction intersecting with the second direction and being parallel to the upper surface of the substrate;
• a second insulating member provided in the stacked body and extending in the second direction to divide the electrode layer in an upper portion of the stacked body in the third direction, and
• a fourth insulating member provided in the stacked body, intersecting with the first members and the second insulating member, and extending in the third direction to divide the electrode layer in the upper portion of the stacked body in the third direction.