Semiconductor memory device including memory pillars and transistor and manufacturing method thereof

A semiconductor memory device comprising:

• a semiconductor substrate including a first surface;
• a first semiconductor layer provided on a first region of the first surface of the semiconductor substrate, the first semiconductor layer including a second surface opposite of and parallel to the first surface of the semiconductor substrate;
• a first transistor provided on the second surface of the first semiconductor layer;
• a second semiconductor layer provided on a second region of the first surface of the semiconductor substrate, the second semiconductor layer including a third surface opposite of and parallel to the first surface of the semiconductor substrate;
• a second transistor provided on the third surface of the second semiconductor layer;
• a stacked body provided on a third region of the first surface of the semiconductor substrate, the stacked body including a plurality of conductors that are stacked one above the other in a first direction and a plurality of memory pillars extending in the first direction;
• a first insulator provided between the first semiconductor layer and the second semiconductor layer;
• a second insulator provided between the first semiconductor layer and the stacked body;
• and
• a third insulator provided between the second semiconductor layer and the stacked body, wherein
• the first semiconductor layer has a length of a lower portion of the first semiconductor layer in a second direction that is smaller than a length of the second surface of the first semiconductor layer in the second direction,
• the lower portion is closer to the semiconductor substrate than the second surface, and
• the second direction is parallel to the first surface of the semiconductor substrate.