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US 10,896,912 B2Granted
Stacked vertical transistor erasable programmable read-only memory and programmable inverter devices
AssigneeInternational Business Machines Corporation
InventorsAlexander Reznicek, Karthik Balakrishnan, Tak Ning, Bahman Hekmatshoartabari
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Abstract
A method for manufacturing a semiconductor device includes forming a first vertical transistor on a semiconductor substrate, and forming a second vertical transistor stacked on the first vertical transistor. In the method, a silicide layer is formed on a first drain region of the first vertical transistor and on a second drain region of the second vertical transistor. The silicide layer electrically connects the first and second drain regions to each other.
Claims13
A method for manufacturing a semiconductor device, comprising:
- forming a first vertical transistor on a semiconductor substrate;
- forming a second vertical transistor stacked on the first vertical transistor;
- and
- forming a silicide layer on a first drain region of the first vertical transistor and on a second drain region of the second vertical transistor, wherein the silicide layer electrically connects the first and second drain regions to each other;
- wherein forming the silicide layer comprises:
- forming a sacrificial layer on the first and second drain regions;
- removing the sacrificial layer to expose the first and second drain regions;
- and
- performing a silicidation process to form the silicide layer.
6 more elements
A method for manufacturing a semiconductor device, comprising:
- forming a first vertical transistor on a semiconductor substrate;
- forming a second vertical transistor stacked on the first vertical transistor;
- and
- forming a silicide layer on a first drain region of the first vertical transistor and on a second drain region of the second vertical transistor, wherein the silicide layer electrically connects the first and second drain regions to each other;
- wherein forming the first vertical transistor comprises:
- forming a bottom source region on a semiconductor substrate;
- forming a first channel region extending vertically from the bottom source region;
- forming the first drain region on an upper portion of the first channel region;
- and
- forming a first gate region around the first channel region;
- wherein forming the second vertical transistor comprises:
- forming the second drain region on an upper portion of the first drain region;
- forming a second channel region extending vertically from the second drain region;
- forming a top source region on an upper portion of the second channel region;
- and
- forming a second gate region around the second channel region;
- wherein the first gate region comprises a first gate metal layer formed on a first high-K dielectric layer, and the second gate region comprises a second gate metal layer formed on a second high-K dielectric layer;
- and
- wherein the first high-K dielectric layer has a greater thickness than the second high-K dielectric layer.
16 more elements
A method for manufacturing a semiconductor device, comprising:
- forming a first vertical transistor on a semiconductor substrate;
- forming a second vertical transistor stacked on the first vertical transistor;
- forming a silicide layer on a first drain region of the first vertical transistor and on a second drain region of the second vertical transistor, wherein the silicide layer electrically connects the first and second drain regions to each other;
- wherein forming the first vertical transistor comprises:
- forming a bottom source region on a semiconductor substrate;
- forming a first channel region extending vertically from the bottom source region;
- forming the first drain region on an upper portion of the first channel region;
- and
- forming a first gate region around the first channel region;
- wherein forming the second vertical transistor comprises:
- forming the second drain region on an upper portion of the first drain region;
- forming a second channel region extending vertically from the second drain region;
- forming a top source region on an upper portion of the second channel region;
- and
- forming a second gate region around the second channel region;
- forming a first dummy gate layer around the first channel region and forming a first dummy gate layer around the first channel region prior to forming the first and second gate regions;
- and
- replacing the first and second dummy gate layers with the first and second gate regions respectively;
- wherein the first and second dummy gate layers comprise different materials from each other.
16 more elements
Dependencies are inferred from the claim text.