Method for forming memory device involving ion implantation of the control gate spacer and wet etching process to expose sidewall of control gate
AssigneeWinbond Electronics Corp.
InventorsHsu-Chi Cho, Cheng-Ta Yang
Life of this patent
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Abstract
A method for forming a memory device is provided. The method includes forming a floating gate on a substrate, and forming a control gate on the floating gate. The method also includes forming a mask layer on the control gate, and forming a spacer on a sidewall of the mask layer, wherein a sidewall of the control gate and a sidewall of the floating gate is covered by the spacer. The method further includes performing an ion implantation process to implant a dopant into a top portion of the spacer, and performing a wet etching process to expose the sidewall of the control gate.
Claims20
A method for forming a memory device, comprising:
- forming a floating gate on a substrate;
- forming a control gate on the floating gate;
- forming a mask layer on the control gate;
- forming a spacer on a sidewall of the mask layer, wherein a sidewall of the control gate and a sidewall of the floating gate is covered by the spacer;
- performing an ion implantation process to implant a dopant into a top portion of the spacer;
- and
- performing a wet etching process to expose the sidewall of the control gate.
A method for forming a memory device, comprising:
- forming a floating gate on a substrate;
- forming a control gate on the floating gate;
- forming a spacer on a sidewall of the control gate;
- performing an ion implantation process to implant a dopant into a top portion of the spacer, wherein after performing the ion implantation process, the top portion of the spacer has a conductivity type that is the same as that of the control gate;
- and
- performing a wet etching process to remove the top portion of the spacer.
A method for forming a memory device, comprising:
- providing a substrate comprising a peripheral circuit region and an array region;
- forming a first control gate and a second control gate on the peripheral circuit region of the substrate, wherein a first trench is between the first control gate and the second control gate;
- forming a spacer on a sidewall of the first trench, wherein a top surface of the spacer is higher than a top surface of the first control gate and a top surface of the second control gate;
- performing an ion implantation process to implant a dopant into the spacer, the first control gate and the second control gate;
- and
- after performing the ion implantation process, performing a wet etching process to expose the sidewall of the first trench.
Dependencies are inferred from the claim text.