Memory structure and manufacturing method thereof

A manufacturing method of a memory structure, comprising:

• forming a first dielectric layer on a substrate;
• forming a pair of separate gate stack structures on the first dielectric layer, wherein each of the gate stack structures comprises:
• a word line, located on the substrate;
• an erase gate, located on the word line;
• and
• a second dielectric layer, located between the word line and the erase gate;
• forming a third dielectric layer on a surface of each of the gate stack structures;
• forming a pair of floating gates between the gate stack structures, wherein each of the floating gates is located on the third dielectric layer on a sidewall of the corresponding gate stack structure, and a top surface of each of the floating gates is lower than a top surface of each of the erase gates;
• forming a doped region in the substrate beside each of the gate stack structures;
• forming a fourth dielectric layer on the substrate, wherein the fourth dielectric layer covers the first dielectric layer, the third dielectric layer and the floating gates;
• and
• forming a control gate on the fourth dielectric layer between the floating gates.