Bulk CMOS devices with enhanced performance and methods of forming the same utilizing bulk CMOS process

An apparatus comprising:

• a device substrate having a top surface;
• a thinned device die comprising a device region and a plurality of bump structures, wherein:
• the device region comprises a back-end-of-line (BEOL) portion with a plurality of connecting layers and a front-end-of-line (FEOL) portion residing over the BEOL portion, wherein the FEOL portion comprises a contact layer and an active layer that resides over the contact layer and has a first component cell;
• and
• the plurality of bump structures are formed at a bottom surface of the BEOL portion and attached to the top surface of the device substrate, wherein the plurality of bump structures are electrically coupled to the FEOL portion via certain ones of the plurality of connecting layers;
• a first mold compound residing over the top surface of the device substrate, surrounding the thinned device die, and extending vertically beyond the thinned device die to define an opening over the thinned device die and within the first mold compound, wherein a top surface of the thinned device die is at the bottom of the opening;
• and
• a second mold compound substantially filling the opening and in contact with the top surface of the thinned device die, wherein a silicon material, which has a resistivity between 5 Ohm-cm and 30000 Ohm-cm, does not exist between the second mold compound and the active layer of the thinned device die.