Circuit overvoltage protection

An electrostatic discharge (ESD) protection circuit, comprising:

• a snapback ESD protection device configured to shunt current of an ESD event to a voltage reference;
• and
• an ESD tail current clamp circuit connected in parallel with the snapback ESD protection device, the ESD tail current clamp circuit configured to shunt tail current of the ESD event to the voltage reference while the snapback ESD protection device is disabled, the ESD tail current clamp circuit including a shunt transistor configured to shunt the tail current to the voltage reference;
• a control terminal;
• and
• control circuitry coupled to the control terminal, the control circuitry configured to disable the shunt transistor while a control signal is asserted at the control terminal.

An ESD tail current clamp circuit, comprising:

• a shunt transistor configured to shunt a tail current of an electrostatic discharge (ESD) event to a voltage reference;
• a first control transistor coupled to a control terminal of the shunt transistor;
• wherein the first control transistor drives a pulse onto the control terminal of the shunt transistor responsive to the ESD event;
• wherein:
• the shunt transistor and the first control transistor route a voltage induced on the control terminal via the pulse to the voltage reference via a body diode of the first control transistor and a drain-source channel of the shunt transistor;
• and
• the shunt transistor remains active responsive to an ESD induced voltage exceeding a threshold voltage of the shunt transistor less a voltage drop across the body diode of the first control transistor.