ESD guard ring with snapback protection and lateral buried layers

An integrated circuit, comprising:

• a semiconductor substrate having a P-type dopant and a top surface defining a circuit region and a peripheral region laterally surrounding the circuit region;
• a diode having a cathode region positioned within the circuit region and adjacent to the peripheral region, the cathode region having an N-type dopant;
• a lateral drain metal oxide semiconductor (LDMOS) transistor positioned within the circuit region and adjacent to the peripheral region, the LDMOS transistor includes a lateral drain region having a top surface spaced below the top surface of the semiconductor substrate and laterally separated from the cathode region, and the lateral drain region having the N-type dopant;
• a peripheral structure positioned within the peripheral region and adjacent to the top surface, the peripheral structure including a first contact region having the P-type dopant, and a second contact region having the N-type dopant, the second contact region interposed laterally between the first contact region and the cathode region, and interposed between the first contact region and the lateral drain region, and a heavily doped region contacting a doped region and positioned within the circuit region, the heavily doped region extends from a third contact region to a buried layer and a heavily doped buried layer disposed in the buried layer.