Wafer-level methods of fabricating semiconductor device packages and related packages

A method of fabricating a semiconductor device package, comprising:

• forming first trenches in streets between first regions of integrated circuitry of a first active surface of a first semiconductor wafer by cutting partially through the first semiconductor wafer;
• placing a first quantity of a dielectric material in contact with the first active surface at least partially surrounding first electrically conductive elements located on the first active surface;
• operatively connecting ends of the first electrically conductive elements to bond pads connected to second regions of integrated circuitry at a second active surface of a second semiconductor wafer with the first quantity of the dielectric material between the first semiconductor wafer and the second semiconductor wafer while the second semiconductor is wafer supported on a first carrier located on a side of the second semiconductor wafer opposite the first semiconductor wafer;
• applying force to the first semiconductor wafer, the second semiconductor wafer, and the first carrier and reflowing portions of the first electrically conductive elements;
• flowing portions of the first quantity of the dielectric material into the first trenches;
• permitting the first electrically conductive elements and the first quantity of the dielectric material to cool;
• removing the first carrier;
• forming second trenches aligned with the streets by cutting entirely through the second semiconductor wafer and partially into the first quantity of the dielectric material;
• placing a second quantity of the dielectric material in contact with a second backside surface of the second semiconductor wafer located on a side of the second semiconductor wafer opposite the second active surface, at least partially surrounding second electrically conductive elements located on the second backside surface and electrically connected to vias of the second semiconductor wafer with the second quantity of the dielectric material;
• operatively connecting ends of the second electrically conductive elements to vias connected to third regions of integrated circuitry of a third active surface of a third semiconductor wafer with the second quantity of the dielectric material interposed between the second semiconductor wafer and the third semiconductor wafer while the third semiconductor wafer is supported on a second carrier located on a side of the third semiconductor wafer opposite the second semiconductor wafer;
• applying force to the first semiconductor wafer, the second semiconductor wafer, the third semiconductor wafer, and the second carrier and reflowing portions of the second electrically conductive elements;
• flowing portions of the second quantity of the dielectric material into the second trenches;
• permitting the second electrically conductive elements and the second quantity of the dielectric material to cool;
• reducing a thickness of the first semiconductor wafer from a side of the first semiconductor wafer opposite the second semiconductor wafer and revealing the portions of the first quantity of the dielectric material in the first trenches;
• removing the second carrier;
• and
• separating the first regions of integrated circuitry from one another, the second regions of integrated circuitry from one another, and the third regions of integrated circuitry from one another at least partially by cutting through portions of the first and second quantities of the dielectric material in the trenches.