Semiconductor package

A method of manufacturing a semiconductor package, the method comprising:

• preparing a frame having a first through-hole, the frame including wiring layers and stacked vias electrically connected to the wiring layers;
• disposing a semiconductor chip in the first through-hole, the semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface disposed opposing the active surface;
• encapsulating the semiconductor chip with a first encapsulant;
• forming a connection structure on the active surface of the semiconductor chip, the connection structure including a redistribution layer electrically connected to the connection pad of the semiconductor chip and a ground pattern layer;
• performing a first sawing process on the frame, the first encapsulant, and a portion of the connection structure, at a boundary of a unit package to form a sawed region;
• filling the sawed region with an insulating material;
• forming a side surface cover layer by performing a second sawing process through the side surface cover layer and at least a portion of the connection structure, at the boundary of the unit package;
• forming a metal layer to cover an upper surface of the first encapsulant, the side surface cover layer, and a portion of a side surface of the connection structure;
• forming an opening of the metal layer by removing a portion of the metal layer to expose a portion of the wiring layers;
• and
• performing a third sawing process for a lower region in a lower portion of the metal layer, at the boundary of the unit package,
• wherein the first sawing process is performed to saw at a first width and the second sawing process is performed to saw at a second width narrower than the first width.

A method of manufacturing a semiconductor package, the method comprising:

• preparing a frame having a first through-hole, the frame including a first frame insulating layer and a first wiring layer and a second wiring layer disposed on both sides of the first frame insulating layer;
• disposing a semiconductor chip in the first through-hole, the semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface disposed opposing the active surface;
• encapsulating the semiconductor chip with a first encapsulant;
• forming a connection structure on the active surface of the semiconductor chip, the connection structure including a redistribution layer electrically connected to the connection pad of the semiconductor chip and a ground pattern layer;
• performing a first sawing process on the frame, the first encapsulant, and a portion of the connection structure, at a boundary of a unit package to form a sawed region;
• filling a sawed region with an insulation material;
• forming a side surface cover layer by performing a second sawing process for the side surface cover layer and at least a portion of the connection structure, at the boundary of the unit package;
• forming a metal layer to cover an upper surface of the first encapsulant, the side surface cover layer, and a portion of a side surface of the connection structure;
• performing a third sawing process for a lower region in a lower portion of the metal layer, at the boundary of the unit package;
• and
• mounting the unit package on a mainboard of an electronic device,
• wherein the first sawing process is performed to saw at a first width and the second sawing process is performed to saw at a second width narrower than the first width.