Integrated circuit saw bow break point
AssigneeNXP B.V.
InventorsAntonius Hendrikus Jozef Kamphuis, Johannes Cobussen, Christian Zenz, Guido Albermann
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Abstract
A saw bow is provided and designed such that the conductors of the saw bow will break at a predictable location when using modern dicing techniques. This results in a break in the circuit provided by the saw bow, with any exposed conductors not being on the die side. Further, by providing a known breaking point in the saw bow, modern dicing techniques such as plasma dicing can be used, thereby allowing for the saw lane to be made narrower, which will in turn increase the number of wafers that can be included on a wafer.
Claims15
A semiconductor wafer having a plurality of semiconductor device die arranged in a grid pattern, the semiconductor wafer comprising:
- a first semiconductor device die;
- a second semiconductor device die, neighboring the first semiconductor device die in the grid pattern and separated from the first semiconductor device die by a dicing lane;
- and
- a first conductor extending from a side of the first semiconductor device die into the dicing lane and extending toward the second semiconductor device die, entering the second semiconductor device die, and ending within a seal ring region of the second semiconductor device die, wherein the first conductor is formed such that a first region of the first conductor located nearer to the first semiconductor device die in the dicing lane has a lower tensile strength than a second region of the first conductor located in the dicing lane nearer to the second semiconductor device die.
A method of providing a saw bow to a semiconductor device die on a wafer, the method comprising:
- forming integrated circuitry within one or more metal layers on a wafer, wherein
- the integrated circuitry is arranged in a grid pattern of a plurality of device die regions including a first semiconductor device die region and a second semiconductor device die region, and
- the first semiconductor device die region is separated from the second semiconductor device die region by a dicing lane;
- and
- forming a first conductor extending from a side of the first semiconductor device die region into the dicing lane and toward the second semiconductor device die region, wherein
- the first conductor is coupled to a metal layer of the one or more metal layers,
- the first conductor ends within a seal ring region of the second semiconductor device die region,
- the first conductor comprises a first region located in the dicing lane nearer to the first semiconductor device die region and a second region located in the dicing lane nearer to the second semiconductor device die region, and
- the first conductor comprises a lower tensile strength in the first region than the second region.
Dependencies are inferred from the claim text.