Power module semiconductor device and inverter equipment, and fabrication method of the power module semiconductor device, and metallic mold
AssigneeRohm Co., Ltd.
InventorToshio Hanada
Life of this patent
Estimating the term…
Abstract
The power module semiconductor device (2) includes: an insulating substrate (10); a first pattern (10a) (D) disposed on the insulating substrate (10); a semiconductor chip (Q) disposed on the first pattern; a power terminal (ST, DT) and a signal terminal (CS, G, SS) electrically connected to the semiconductor chip; and a resin layer (12) configured to cover the semiconductor chip and the insulating substrate. The signal terminal is disposed so as to be extended in a vertical direction with respect to a main surface of the insulating substrate.
Claims14
An inverter apparatus comprising a semiconductor device and a circuit substrate on which the semiconductor device is mounted,
- the semiconductor device comprising:
- a first metal pattern;
- a second metal pattern;
- a third metal pattern;
- a first transistor element disposed on or over the first metal pattern;
- a second transistor element disposed on or over the first metal pattern;
- a first upper surface plate electrode electrically connected to the first transistor element and the second transistor element;
- a first wire connected between a control electrode of the first transistor element and the second metal pattern;
- a second wire connected between a control electrode of the second transistor element and the third metal pattern;
- a first rectangular parallelepiped electrode formed to connect between the first transistor element and the first upper surface plate electrode;
- a second rectangular parallelepiped electrode formed to connect between the second transistor element and the first upper surface plate electrode;
- a resin layer formed to cover the first transistor element and the second transistor element, the resin layer having an upper main surface, a lower main surface, and peripheral edges joining the upper main surface and the lower main surface;
- a signal control terminal electrically connected to the first transistor element and the second transistor element;
- and
- a terminal receiving substrate configured to receive the signal control terminal,
- wherein
- a plurality of the semiconductor devices is mounted on the circuit substrate and the semiconductor devices are disposed to be adjacent to one another, and
- the plurality of the semiconductor devices are mounted on the circuit substrate in a manner that a plurality of the signal control terminals respectively extending from the semiconductor devices penetrate the circuit substrate and are received by the terminal receiving substrate.
Dependencies are inferred from the claim text.