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US 10,896,857 B2Granted
Vertical field effect transistors
AssigneeInternational Business Machines Corporation
InventorsBrent A. Anderson, Edward J. Nowak
Life of this patent
Estimating the term…
Abstract
Vertical field effect transistors (FETs) with minimum pitch and methods of manufacture are disclosed. The structure includes at least one vertical fin structure and gate material contacting with the at least one vertical fin structure. The structure further includes metal material in electrical contact with the ends of the at least one vertical fin.
Claims14
A method, comprising:
- forming source and drain contacts at ends of at least one vertical fin structure of a plurality of vertical fin structures by deposition of metal material in electrical contact with silicide regions,
- wherein each of the plurality of vertical fin structures comprises a wide lower portion on an insulator layer and a narrow body portion on the wide lower portion.
A semiconductor structure, comprising:
- source and drain contacts at ends of at least one vertical fin structure of a plurality of vertical fin structures, the source and drain contacts comprising metal material in electrical contact with silicide regions,
- wherein each of the plurality of vertical fin structures comprises a wide lower portion on an insulator layer and a narrow body portion on the wide lower portion.
Dependencies are inferred from the claim text.