Asymmetric gate spacer formation using multiple ion implants

A method of forming an asymmetric gate spacer, the method comprising:

• providing a gate structure atop a substrate;
• providing a first gate spacer along a first sidewall of the gate structure, and providing a second gate spacer along a second sidewall of the gate structure;
• performing a first ion implant to the first gate spacer, the first ion implant disposed at a first non-zero angle of inclination with respect to a perpendicular to a plane of the substrate, wherein the first ion implant is performed at a temperature greater than 500° C.;
• performing a second ion implant to the second gate spacer, the second ion implant disposed at a second non-zero angle of inclination with respect to the perpendicular to the plane of the substrate, wherein the second ion implant is performed at a temperature between approximately 15° C. and 30° C.;
• and
• etching the first gate spacer and the second gate spacer, wherein just the second gate spacer is removed selective to a top surface of the substrate and to a sidewall surface of the second sidewall of the gate structure.

A method of forming an asymmetric gate spacer, the method comprising:

• providing a dummy gate structure atop a substrate;
• providing a first gate spacer along a first sidewall of the dummy gate structure, and providing a second gate spacer along a second sidewall of the dummy gate structure;
• performing a first ion implant to the first gate spacer, the first ion implant disposed at a first non-zero angle of inclination with respect to a perpendicular to a plane of the substrate, wherein the first ion implant is performed at a platen temperature greater than 500° C.;
• performing a second ion implant to the second gate spacer, the second ion implant disposed at a second non-zero angle of inclination with respect to the perpendicular to the plane of the substrate, wherein the second ion implant is performed at a temperature between approximately 15° C. and 30° C.;
• and
• etching the first gate spacer and the second gate spacer, wherein just the second gate spacer is removed selective to a top surface of the substrate and to a sidewall surface of the second sidewall of the dummy gate structure.