US 10,896,854 B2Granted

Forming fins utilizing alternating pattern of spacers

AssigneeInternational Business Machines Corporation

InventorsKangguo Cheng, Peng Xu

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Abstract

A method of forming a semiconductor structure includes forming a first pattern of alternating spacers of a first material and a second material on a semiconductor substrate, forming a second pattern of the alternating spacers of the first material and the second material by selectively removing at least a portion of at least one of one or more of the spacers of the first material and one or more of the spacers of the second material to form a remaining pattern of spacers of the first material and the second material on the semiconductor substrate, and transferring the second pattern of the spacers of the first material and the second material to the semiconductor substrate to form two or more fins in the semiconductor substrate by etching the semiconductor substrate selective to the first material and the second material.

Claims20

Dependent claims

A semiconductor structure, comprising:

a substrate;
and
two or more fins formed in the substrate in a given pattern, each of the two or more fins having a pad layer formed on a top surface thereof and a spacer formed over a top of the pad layer;
wherein the given pattern comprises alternating spacers of a first material and a second material with at least a portion of one of the spacers removed via a cut mask;
wherein the alternating spacers comprise a first spacer formed over a first one of the two or more fins that comprises the first material but not the second material adjacent at least a second spacer formed over a second one of the two or more fins that comprises the second material but not the first material, the second material being different than the first material;
wherein a top surface of the first spacer is substantially coplanar with a top surface of the second spacer;
and
wherein the pad layer of each of the two or more fins is a third material different than the first material and the second material.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/468,394Filed 24 Mar 2017 · division
Priority: 29 Jun 2016
Published: US 2018/0005898 A14 Jan 2018
Granted: 19 Jan 2021
Term ends: Not estimatedThe source records don’t support an estimate.

Classification16 codes

H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
H10D 64/015
Manufacture or treatment: removing at least parts of gate spacers, e.g. disposable spacers
H10D 64/021
Manufacture or treatment: using multiple gate spacer layers, e.g. bilayered sidewall spacers
H10D 84/0147
The components including insulated gates, e.g. IGFETs: manufacturing their gate sidewall spacers