Techniques for revealing a backside of an integrated circuit device, and associated configurations

A computing device comprising:

• a circuit board;
• and
• a die coupled with the circuit board on a front side of the die, the die including:
• a plurality of fins extending from a backside of the die into a device layer of the die, wherein the plurality of fins are a semiconductor material;
• one or more transistor layers in the device layer and coupled to one or more fins of the plurality of fins to form one or more transistors;
• an interconnect layer coupled to the backside of the integrated circuit;
• and
• one or more backside vias extending to the device layer of the die from the interconnect layer to route signals to or from the one or more transistors,
• wherein the die does not include a semiconductor substrate that connects the plurality of fins or is located between the plurality of fins and the interconnect layer.