Resonant LC tank package and method of manufacture
AssigneeIntel IP Corporation
InventorsSaravana Maruthamuthu, Andreas Augustin, Andreas Wolter
Life of this patent
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Abstract
A package on a die having a low resistive substrate, wherein the package comprises an inductor on low-k dielectric and a capacitor on high-k dielectric. The stacked arrangement having different dielectric materials may provide an inductor having a high Q-factor while still having a high capacitance density. In addition, moving the inductor from the die to the package and fabricating the high density capacitor on the package reduces the silicon area required permitting smaller RF/analog blocks on the chip.
Claims25
An LC package fabricated on a die having a low-resistive substrate, comprising:
- an inductor fabricated on low-k dielectric;
- a capacitor fabricated on high-k dielectric, wherein the capacitor is positioned between the inductor and the die, the capacitor including:
- a first plate;
- a second plate;
- and
- wherein the high-k dielectric is located in a gap between the first plate and the second plate;
- and
- a via electrically connecting the inductor with one or more of the first plate or the second plate;
- a dielectric spacer;
- and
- wherein the inductor and the capacitor are fabricated over the dielectric spacer such that the dielectric spacer is positioned between the die and the inductor and capacitor.
A circuit on a chip, comprising:
- a die, including:
- a low-resistive substrate, and
- at least one dielectric layer fabricated over the low-resistive substrate;
- and
- a package fabricated on the die, including:
- an inductor fabricated on low-k dielectric;
- a capacitor fabricated on high-k dielectric, wherein the capacitor is positioned between the inductor and the die, the capacitor including:
- a first plate;
- a second plate;
- and
- wherein the high-k dielectric is located in a gap between the first plate and the second plate;
- a via electrically connecting the inductor with one or more of the first plate or the second plate;
- and
- a dielectric spacer;
- wherein the inductor and the capacitor are fabricated over the dielectric spacer such that the dielectric spacer is positioned between the die and the inductor and capacitor.
A package for an electronic device including a die having a low-resistive substrate, the package comprising:
- an inductor included in one or more layers of a low-k dielectric;
- a capacitor included in one or more layers of a high-k dielectric, the capacitor including:
- a first plate;
- a second plate;
- wherein the high-k dielectric is located in a gap between the first plate and the second plate, and at least one of the first plate or the second plate are located between the inductor and the die;
- a first via electrically connecting the inductor with one or more of the first plate or the second plate;
- a dielectric spacer;
- and
- wherein the inductor and the capacitor are fabricated over the dielectric spacer such that the dielectric spacer is positioned between the die and the inductor and capacitor.
Dependencies are inferred from the claim text.