Semiconductor memory device and NAND-type flash memory erase method
AssigneeWinbond Electronics Corp.
InventorNaoaki Sudo
Life of this patent
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Abstract
The present invention provides a semiconductor memory device capable of performing rapid erasing while reducing power consumption. In the flash memory of the present invention, the voltage of the P well is detected by the voltage detecting unit 200 during the erasing operation. When the voltage is lower than the threshold value, it is determined that the off leakage current of the selection transistor of the non-selection block is large, and the voltage of the global word line at the time of applying the next erase pulse is increased. When the voltage is above the threshold value, it is determined that the off leakage current is small, and the voltage of the global word line at the time of applying the next erase pulse is maintained.
Claims16
An erase method for NAND-type flash memory, comprising:
- based on address information, applying a first voltage to a gate of a first selection transistor connected to each word line of a memory cell to select a block, applying a second voltage to a gate of a second selection transistor connected to each word line of the memory cell to unselect a block, and applying a third voltage to a source/drain of the first and second selection transistors;
- detecting a voltage of a well region when an erase pulse is applied;
- and
- controlling the third voltage based on the detected voltage.
An erase method for NAND-type flash memory, comprising:
- based on address information, applying a first voltage to a gate of a first selection transistor connected to each word line of a memory cell to select a block, applying a second voltage to a gate of a second selection transistor connected to each word line of the memory cell to unselect a block, and applying a third voltage to a source/drain of the first and second selection transistors;
- detecting off-leakage current of the selection transistor based on detecting a voltage of a well region when an erase pulse is applied;
- and
- controlling the third voltage based on the detected off-leakage current.
A semiconductor memory device comprising:
- a memory cell array comprising a plurality of memory cells;
- a selection member comprising a selection transistor connected to each word line of the plurality of memory cells, wherein according to address information, the selection member applies a first voltage to a gate of a first selection transistor to select a block, and applies a second voltage to a gate of a second selection transistor to unselect a block;
- an erase member applying a third voltage to a source/drain of the first and second selection transistors, and applying an erase voltage to a well region to erase a selected block,
- wherein the erase member further comprises:
- a detection member detecting a voltage of the well region after the erase pulse is applied;
- and
- a control member controlling the third voltage based on the voltage detected by the detection member.
Dependencies are inferred from the claim text.