US 10,896,735 B2Granted

Semiconductor memory device

AssigneeToshiba Memory Corporation

InventorsBushnaq Sanad, Noriyasu Kumazaki, Yuzuru Shibazaki

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Abstract

According to one embodiment, a semiconductor memory device includes: a memory cell array including a first memory cell, a first word line, a first circuit coupled to the first word line, a first driver used for a write operation and a read operation, a second driver used for an erase operation, and a voltage generator. The first circuit includes: a second circuit capable of electrically coupling the first word line and a first interconnect; a third circuit capable of electrically coupling the first interconnect and a second interconnect; a fourth circuit capable of electrically coupling the second interconnect and the first driver in the write and read operations; and a fifth circuit capable of electrically coupling the second interconnect and the second driver in the erase operation.

Claims20

Dependent claims

A semiconductor memory device comprising:

a memory cell array including a first memory cell;
a first word line coupled to a gate of the first memory cell;
a first circuit coupled to the first word line;
a first driver used for a write operation and a read operation;
a second driver used for an erase operation;
and
a voltage generator respectively coupled to the first and second drivers,
wherein the first circuit includes:
a second circuit capable of electrically coupling the first word line and a first interconnect in the write operation, the read operation, and the erase operation in which the first word line is selected;
a third circuit capable of electrically coupling the first interconnect and a second interconnect in the write operation, the read operation, and the erase operation;
a fourth circuit capable of electrically coupling the second interconnect and the first driver in the write operation and the read operation;
and
a fifth circuit capable of electrically coupling the second interconnect and the second driver in the erase operation.

10 more elements

A semiconductor memory device comprising:

a memory cell array including a first memory cell;
a first word line coupled to a gate of the first memory cell;
a first circuit coupled to the first word line;
a first driver used for a write operation and a read operation;
a second driver used for an erase operation;
and
a voltage generator respectively coupled to the first and second drivers,
wherein the first circuit includes:
a second circuit capable of electrically coupling the first word line and a first interconnect in the write operation, the read operation, and the erase operation, in which the first word line is selected;
a third circuit capable of electrically coupling the first interconnect and a second interconnect in the write operation, the read operation, and the erase operation;
a fourth circuit capable of electrically coupling the second interconnect and the first driver in the write operation;
a fifth circuit capable of electrically coupling the second interconnect and the first driver in the read operation;
and
a sixth circuit capable of electrically coupling the second interconnect and the second driver in the erase operation.

11 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/564,223Filed 9 Sep 2019
Priority: JP 2018-23580017 Dec 2018
Published: US 2020/0194077 A118 Jun 2020
Granted: 19 Jan 2021
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G11C 16/12
Programming or data input circuits: programming voltage switching circuits
G11C 16/0483
Using variable threshold transistors, e.g. FAMOS: comprising cells having several storage transistors connected in series
G11C 16/08
Auxiliary circuits, e.g. for writing into memory: address circuits; Decoders; Word-line control circuits
G11C 16/24
Auxiliary circuits, e.g. for writing into memory: bit-line control circuits