Semiconductor memory device and method of operating the same
AssigneeSK hynix Inc.
InventorIn Gon Yang
Life of this patent
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Abstract
Provided herein may be a semiconductor memory device and a method of operating the semiconductor memory device to program a selected physical page of the semiconductor memory device. The method may include performing a plurality of program loops. Each of the program loops may include: applying a bit line voltage based on data input to a page buffer of the semiconductor memory device; applying a two-step program pulse to a word line coupled to the selected physical page; performing a program verify operation on the selected physical page using a double verify scheme; and determining a bit line voltage to be applied in a subsequent program loop based on a result of the program verify operation.
Claims12
A method of operating a semiconductor memory device to program a selected physical page of the semiconductor memory device, the method comprising performing a plurality of program loops,
- wherein each of the program loops comprises:
- applying a bit line voltage based on data input to a page buffer of the semiconductor memory device;
- applying a two-step program pulse to a word line coupled to the selected physical page;
- performing a program verify operation on the selected physical page using a double verify scheme;
- and
- determining a bit line voltage to be applied in a subsequent program loop based on a result of the program verify operation,
- wherein the performing of the program verify operation on the selected physical page using the double verify scheme comprises:
- applying a verify voltage to the word line, the verify voltage corresponding to at least one program state, and performing an auxiliary verify operation using an auxiliary evaluation time;
- and
- applying the verify voltage to the word line, and performing a main verify operation using a main evaluation time, and
- wherein the auxiliary evaluation time is shorter than the main evaluation time.
A semiconductor memory device comprising:
- a memory cell array including a plurality of physical pages;
- a peripheral circuit configured to perform a program operation on a selected physical page among the plurality of physical pages, the program operation including a plurality of program loops;
- and
- a control logic configured to control the program operation of the peripheral circuit,
- wherein, during a program loop of the program operation of the selected physical page, the control logic controls the peripheral circuit to apply a two-step program pulse to a word line coupled to the selected physical page and perform a program verify operation on the selected physical page using a double verify scheme, and
- wherein, to perform the program verify operation on the selected physical page using the double verify scheme, the control logic controls the peripheral circuit to apply a verify voltage corresponding to at least one program state to the word line for an auxiliary evaluation time, and apply the verify voltage to the word line for a main evaluation time longer than the auxiliary evaluation time.
Dependencies are inferred from the claim text.