Semiconductor memory device and method of controlling the same
AssigneeToshiba Memory Corporation
InventorsKeita Kimura, Hidehiro Shiga
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device comprises: a memory transistor; a first wiring connected to a gate electrode of the memory transistor; and a control device that executes a read operation to read data of the memory transistor and a write operation to write data in the memory transistor. In the read operation or the write operation, the control device: increases a voltage of the first wiring to a first voltage from a first timing to a second timing; and adjusts a length from the first timing to the second timing corresponding to at least one of a voltage of the first wiring, a current of the first wiring, and an amount of charge flowed through the first wiring.
Claims21
A semiconductor memory device comprising:
- a memory transistor;
- a first wiring connected to a gate electrode of the memory transistor;
- and
- a control device that executes a read operation to read data of the memory transistor and a write operation to write data in the memory transistor, wherein
- in the read operation or the write operation, the control device:
- increases a voltage of the first wiring to a first voltage from a first timing to a second timing;
- and
- adjusts a length from the first timing to the second timing corresponding to at least one of a voltage of the first wiring, a current of the first wiring, and an amount of charge flowed through the first wiring, and wherein
- in the read operation, the control device;
- increases the voltage of the first wiring to the first voltage from the first timing to the second timing;
- decreases the voltage of the first wiring to a second voltage from the second timing to a third timing, and
- when a length from the first timing to the second timing is defined as a first length in case that the voltage of the first wiring at the first timing is a first initial voltage, and
- a length from the first timing to the second timing is defined as a second length in case that the voltage of the first wiring at the first timing is a second initial voltage smaller than the first initial voltage and substantially equal to a ground voltage,
- the control device sets the second length larger than the first length.
A method of controlling a semiconductor memory device,
- the semiconductor memory device comprising:
- a memory transistor;
- a first wiring connected to a gate electrode of the memory transistor;
- and
- a control device that executes a read operation to read data of the memory transistor and a write operation to write data in the memory transistor, wherein
- in the read operation or the write operation, the control device:
- increases a voltage of the first wiring to a first voltage from a first timing to a second timing;
- and
- adjusts a length from the first timing to the second timing corresponding to at least one of a voltage of the first wiring, a current of the first wiring, and an amount of charge flowed through the first wiring, wherein
- in the read operation, the control device:
- increases the voltage of the first wiring to the first voltage from the first timing to the second timing;
- decreases the voltage of the first wiring to a second voltage from the second timing to a third timing, and
- when a length from the first timing to the second timing is defined as a first length in case that the voltage of the first wiring at the first timing is a first initial voltage, and
- a length from the first timing to the second timing is defined as a second length in case that the voltage of the first wiring at the first timing is a second initial voltage smaller than the first initial voltage and substantially equal to aground voltage,
- the control device sets the second length larger than the first length.
A semiconductor memory device comprising:
- a memory transistor;
- a first wiring connected to a gate electrode of the memory transistor;
- and
- a control device that executes a read operation to read data of the memory transistor and a write operation to write data in the memory transistor, wherein
- in the read operation or the write operation, the control device:
- increases a voltage of the first wiring to a first voltage from a first timing to a second timing;
- and
- adjusts a length from the first timing to the second timing corresponding to at least one of a voltage of the first wiring, a current of the first wiring, and an amount of charge flowed through the first wiring, wherein
- in the read operation, the control device:
- increases the voltage of the first wiring to the first voltage from the first timing to the second timing;
- decreases the voltage of the first wiring to a second voltage from the second timing to a third timing, and
- when a length from the first timing to the second timing is defined as a first length in case that the voltage of the first wiring at the first timing is a first initial voltage, and
- a length from the first timing to the second timing is defined as a second length in case that the voltage of the first wiring at the first timing is a second initial voltage smaller than the first initial voltage,
- the control device sets the second length larger than the first length, and
- when the control device starts increasing the voltage of the first wiring to the first voltage, the first initial voltage and the second initial voltage are different from each other.
Dependencies are inferred from the claim text.