US 10,896,732 B2Granted

Semiconductor memory device

AssigneeToshiba Memory Corporation

InventorMikiko Yagi

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Abstract

A semiconductor memory device according to the embodiments includes a first laminated body, a second laminated body, an intermediate insulation layer, and a columnar body. The intermediate insulation layer is positioned between the first laminated body and the second laminated body. A plurality of conductive layers of the second laminated body include a first conductive layer which is positioned closest to the intermediate insulation layer among the plurality of conductive layers of the second laminated body. The first conductive layer has a main body part having a first end surface facing the columnar body, and a protrusion part which protrudes from the main body part to the first laminated body, and has a second end surface facing the columnar body. The first end surface and the second end surface are continuous with each other.

A semiconductor memory device comprising:

a first laminated body including a plurality of conductive layers and a plurality of insulation layers alternately laminated in a first direction;
a second laminated body provided above the first laminated body and including a plurality of conductive layers and a plurality of insulation layers alternately laminated in the first direction;
an intermediate insulation layer provided between the first laminated body and the second laminated body and having a thickness in the first direction thicker than that of one insulation layer among the plurality of insulation layers of the first laminated body;
a columnar body extending in the first direction through the first laminated body, the intermediate insulation layer, and the second laminated body, and including a semiconductor layer;
a charge accumulation film provided between the semiconductor layer and the plurality of conductive layers of the first laminated body and between the semiconductor layer and the plurality of conductive layers of the second laminated body,
wherein the columnar body includes a first portion and a second portion provided on the first portion,
a first width in a second direction crossing the first direction of an upper end of the first portion is larger than a second width in the second direction of the lower end of the second portion,
the first portion extending through the first laminated body and extending in the intermediate insulation layer,
the second portion extending through the second laminated body and extending in the intermediate insulation layer,
a first conductive layer, a lowermost layer among the plurality of the conductive layers of the second laminated body, includes a first part which is provided above the intermediate insulation layer and has a first surface facing the second portion of the columnar body in the second direction, and a second part which protrudes from the first part to the first laminated body, and has a second surface facing the second portion of the columnar body in the second direction, and
the first end surface and the second end surface are continuous with each other.

8 more elements

Facts

Application

16/288,141Filed 28 Feb 2019

Priority

JP 2018-1654564 Sep 2018

Published

US 2020/0075100 A15 Mar 2020

Granted

19 Jan 2021

Term ends

Not estimatedThe source records don’t support an estimate.

Classification9 codes

G11C 16/0408
Using variable threshold transistors, e.g. FAMOS: comprising cells containing floating gate transistors
G11C 16/0466
Using variable threshold transistors, e.g. FAMOS: comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon…
H10B 41/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35
Characterised by the memory core region: with a cell select transistor, e.g. NAND

Abstract

Claims19