Content addressable memory circuits with threshold switching memristors
AssigneeHewlett Packard Enterprise Development LP
InventorsCan Li, Catherine Graves, John Paul Strachan
Life of this patent
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Abstract
A content addressable memory (CAM) structure is provided. The CAM comprises a plurality of CAM cells communicatively coupled to processing circuitry. A plurality of threshold switching (TS) memristors are included, each configured to connect to a one of the plurality of CAM cells, with the first end connected to the CAM cell and the second connected to a match line. A discharge transistor is included and configured to discharge any charge on the match line in response to the CAM receiving a command to perform a search.
Claims20
A content addressable memory (CAM) comprising:
- a processing circuitry;
- an array of a plurality of CAM cells communicatively coupled to the processing circuitry;
- a plurality of threshold switching (TS) memristors, at least one TS memristor configured to connect to each of the plurality of CAM cells;
- each TS memristor comprising one of a diffusive memristor, a metal-insulator transition (MIT) device, a Zener diode, a mixed ionic-electronic conducting (MIEC) device;
- each of the TS memristors comprising a first end connected to a CAM cell of the plurality of CAM cells and a second end connected to a match line;
- and
- a discharge transistor connected to the match line, the discharge transistor configured to discharge any charge on the match line in response to the CAM receiving a command to perform a search.
A device comprising:
- a processing circuitry;
- a communications circuitry communicatively coupled to the processing circuitry;
- a content addressable memory (CAM) communicatively coupled to the processing circuitry and the communications circuitry, the CAM comprising:
- an array of a plurality of CAM cells communicatively coupled to a control circuitry of the CAM;
- a plurality of threshold switching (TS) memristors, at least one TS memristor configured to connect to each of the plurality of CAM cells;
- each TS memristor comprising one of a diffusive memristor, a metal-insulator transition (MIT) device, a Zener diode, a mixed ionic-electronic conducting (MIEC) device;
- each of the TS memristors comprising a first end connected to a CAM cell of the plurality of CAM cells and a second end connected to a match line;
- and
- a discharge transistor connected to the match line, the discharge transistor configured to discharge any charge on the match line in response to the CAM receiving a command to perform a search.
A content addressable memory (CAM) comprising:
- an array of a plurality of CAM cells, each CAM cell comprising:
- a high side comprising:
- a first memristor having a first end connected to a high data line and a second end connected to a high-side common node;
- a first switching transistor having a first side connected to a low data line and a second side connected to the high-side common ground;
- and
- a first TS memristor having a first end connected to a match line and a second end connected to the high-side common node;
- a low side comprising:
- a second memristor having a first end connected to the high data line and a second end connected to a low-side common node;
- a second switching transistor having a first side connected to the low data line and a second side connected to the low-side common ground;
- and
- a second TS memristor having a first end connected to the match line and a second end connected to the low-side common node;
- and
- a discharge transistor connected to the match line, the discharge transistor configured to discharge any charge on the match line in response to the CAM receiving a command to perform a search.
Dependencies are inferred from the claim text.