Method of writing data in nonvolatile memory device, with divided subpages or subblocks, and method of erasing data in nonvolatile memory device with divided subpages or subblocks

A nonvolatile memory device comprising:

• a memory cell array including a plurality of cell strings formed in a vertical direction,
• wherein each of the plurality of cell strings includes:
• a string selection transistor connected to a bitline and a string selection line;
• a plurality of memory cells disposed in the vertical direction between the string selection transistor and a common source line, the plurality of memory cells being connected to a plurality of wordlines, respectively;
• and
• a channel structure penetrating the string selection line and the plurality of wordlines that are stacked in the vertical direction, the channel structure including a resistive film, a channel layer surrounding the resistive film, and an insulation film surrounding the channel layer;
• and
• a control circuit configured to perform a data writing operation by dividing a program target page into a plurality of subpages, sequentially performing a program operation on the plurality of subpages, and performing a program verification operation on the program target page including the plurality of subpages at the same time,
• wherein the program target page is connected to one of the plurality of wordlines, and each of the plurality of subpages includes memory cells that are physically spaced apart from one another,
• wherein the control circuit is configured to further perform a data erasing operation by dividing an erase target block into a plurality of subblocks, sequentially performing an erase operation on the plurality of subblocks, and performing an erase verification operation on the erase target block including the plurality of subblocks at the same time,
• wherein the erase target block is connected to at least one of the plurality of wordlines, and
• wherein a number of the plurality of subpages is different from a number of the plurality of subblocks.

A nonvolatile memory device comprising:

• a memory cell array including a plurality of cell strings formed in a vertical direction, wherein each of the plurality of cell strings includes;
• a string selection transistor connected to a bitline and a string selection line;
• a plurality of memory cells disposed in the vertical direction between the string selection transistor and a common source line, the plurality of memory cells being connected to a plurality of wordlines, respectively;
• and
• a channel structure penetrating the string selection line and the plurality of wordlines that are stacked in the vertical direction, the channel structure including a resistive film, a channel layer surrounding the resistive film, and an insulation film surrounding the channel layer;
• and
• a control circuit configured to perform a data writing operation by dividing a program target page into a plurality of subpages, sequentially performing a program operation on the plurality of subpages, and performing a program verification operation on the program target page including the plurality of subpages at the same time,
• wherein the program target page is connected to one of the plurality of wordlines, and each of the plurality of subpages includes memory cells that are physically spaced apart from one another,
• wherein the control circuit is configured to further perform a data erasing operation by dividing an erase target block into a plurality of subblocks, sequentially performing an erase operation on the plurality of subblocks, and performing an erase verification operation on the erase target block including the plurality of subblocks at the same time,
• wherein the erase target block is connected to at least one of the plurality of wordlines, and
• wherein a number of the plurality of subpages and a number of the plurality of subblocks are determined based on a peak limit current of the nonvolatile memory device.