US 10,896,724 B2 · Non-volatile storage system with reduced program transfers

Abstract

A memory system comprises a plurality of memory dies and a controller (or other control circuit) connected to the memory dies. To reduce the time it takes for the memory system to program data and make that programmed data available for reading by a host (or other entity), as well as persistently store the data in a compact manner that efficiently uses space in the memory system, the data is concurrently programmed as single bit per memory cell (fast programming) and multiple bits per memory cell (compact storage). To accomplish this programming strategy, the controller concurrently transfers data to be programmed to a first memory die and a second memory die. The transferred data is programmed in the first memory die at a single bit per memory cell and in the second memory die at multiple bits per memory cell.

Claims19

Dependent claims

An apparatus, comprising:

a plurality of memory dies each having non-volatile memory cells;
and
a control circuit connected to the memory dies, the control circuit is configured to concurrently transfer first data to a first temporary location on a first memory die of the plurality of memory dies and to a second temporary location on a second memory die of the plurality of memory dies as a common data transfer of the first data, the control circuit is further configured to program the transferred first data of the common data transfer from the first temporary location to non-volatile memory cells on the first memory die at a first density per memory cell and program the transferred first data of the common data transfer from the second temporary location to non-volatile memory cells on the second memory die at a second density per memory cell.

A method, comprising:

asserting a command for single bit per memory cell programming on a signal bus connected to multiple memory dies;
transferring a first address on the signal bus, the first address pertains to a first location in the multiple memory dies;
asserting a command for multiple bit per memory cell programming on the signal bus;
transferring a second address on the signal bus, the second address pertains to a second location in the multiple memory dies;
transferring a data set on the signal bus to one or more temporary locations in the multiple memory dies;
and
asserting a program command on the signal bus that causes the data set to be programmed from the one or more temporary locations as both single bit per memory cell at the first location in the multiple memory dies and as multiple bit per memory cell at the second location in the multiple memory dies both in response to one transferring of the data set on the signal bus.

4 more elements

Dependencies are inferred from the claim text.

Non-volatile storage system with reduced program transfers

Life of this patent

Non-volatile storage system with reduced program transfers

Life of this patent

Abstract

Claims19