Integrated assemblies having sense-amplifier-circuitry distributed amongst two or more locations, and having circuitry configured to isolate local column-select-structures from a global structure

An integrated assembly, comprising:

• a first array of first memory cells;
• a second array of second memory cells;
• first digit lines extending along columns of the first array;
• second digit lines extending along columns of the second array;
• sense-amplifier-circuitry configured to comparatively couple the first digit lines with the second digit lines;
• the sense-amplifier-circuitry being subdivided amongst at least four patch locations;
• a first of the at least four patch locations having a first portion of the sense-amplifier-circuitry and having a first local column-select-structure;
• a second of the at least four patch locations having a second portion of the sense-amplifier-circuitry and having a second local column-select-structure;
• a third of the at least four patch locations having a third portion of the sense-amplifier-circuitry and having a third local column-select-structure;
• a fourth of the at least four patch locations having a fourth portion of the sense-amplifier-circuitry and having a fourth local column-select-structure;
• a first column-select-bus extending from decoder-circuitry to the first and second local column-select-structures;
• the first column-select-bus being selectively coupled to the first local column-select-structure through a first switch, and being selectively coupled to the second local column-select-structure through a second switch;
• and
• a second column-select-bus extending from the decoder-circuitry to the third and fourth local column-select-structures;
• the second column-select-bus being selectively coupled to the third local column-select-structure through a third switch, and being selectively coupled to the fourth local column-select-structure through a fourth switch.

An integrated assembly, comprising:

• a base comprising sense-amplifier-circuitry, the sense-amplifier-circuitry being subdivided amongst at least two spaced-apart patch locations;
• each of the patch locations including a SA-O region and a SA-E region;
• a first local column-select-structure associated with the first patch location and a second local column-select-structure associated with the second patch location;
• a column-select-bus extending from decoder circuitry to the first and second local column-select-structures;
• the column-select-bus being selectively coupled to the first local column-select-structure through a first switch, and being selectively coupled to the second local column-select-structure through a second switch;
• a first deck over the base;
• the first deck comprising a first portion of a first array of first memory cells, and comprising a first portion of a second array of second memory cells;
• a second deck over the first deck;
• the second deck comprising a second portion of the first array of the first memory cells, and comprising a second portion of the second array of the second memory cells;
• first digit lines associated with the first array;
• second digit lines associated with the second array;
• and
• the first and second digit lines being comparatively coupled with one another through the sense-amplifier-circuitry.