Controller architecture for reducing on-die capacitance
AssigneeSeagate Technology LLC
InventorNitin Kumar Chhabra
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Abstract
The disclosed controller includes a DDR architecture that includes a dual-channel interface designed to include DQS IO ports configured to generate a first DQS signal that is a distance of substantially 0.125 times the period of a clock signal (ΔT denoting the 0.125 of the period of the clock signal) ahead of a rising edge of the clock signal and a second DQS signal that is a distance of substantially 0.125 times the period of the clock signal behind the rising edge of a clock signal. If ΔT is more than a tDQSS then ΔT is set to tDQSS, where tDQSS is a maximum allowable time between either DQS signal and the rising edge of the clock signal.
Claims20
A method of operating a dual channel double data rate (DDR) interface to access a data storage device comprising:
- setting a delay (ΔT) equal to 0.125 times a period of a clock signal generated by a controller for the DDR interface;
- inserting a first buffer after a divergent point in the controller such that a first delay between a first one of two channels and the clock signal is equal to ΔT on one side of the clock signal;
- inserting a second buffer after the divergent point in the controller such that a second delay between a second one of the two channels and the clock signal is equal to ΔT on an opposite side of the clock signal;
- and
- performing input/output (IO) operations using the dual-channel DDR interface, wherein the first one of the two channels accesses a first memory module of the data storage device using the first buffer and the second one of the two channels accesses a second memory module of the data storage device using the second buffer.
A dual-channel DDR controller for a data storage device, comprising:
- a first channel to perform input/output (IO) operations to access a first memory module of the data storage device;
- a second channel to perform IO operations to access a second memory module of the data storage device;
- and
- a clock generating a clock signal, the clock signal to:
- set a delay (ΔT) equal to 0.125 times a period of the clock signal;
- insert a first buffer after a divergent point in the controller such that a first delay between the first channel and the clock signal is equal to ΔT on one side of the clock signal;
- and
- insert a second buffer after the divergent point in the controller such that a second delay between a second one of the two channels and the clock signal is equal to ΔT on an opposite side of the clock signal.
A method of determining die capacitance required for a dual channel double data rate (DDR) interface to access a data storage device comprising:
- setting a delay (ΔT) equal to 0.125 times a period of a clock signal generated by a controller for the DDR interface;
- inserting a first buffer after a divergent point in the controller such that a first delay between a first one of two channels and the clock signal is equal to ΔT on one side of the clock signal;
- inserting a second buffer after the divergent point in the controller such that a second delay between a second one of the two channels and the clock signal is equal to ΔT on an opposite side of the clock signal;
- and
- performing signal and power integrity simulations using the buffered controller for the DDR interface, wherein the first one of the two channels accesses a first memory module of the data storage device using the first buffer and the second one of the two channels accesses a second memory module of the data storage device using the second buffer;
- calculating a maximum current (IMAX) to be drawn by the DDR interface using the performed simulations;
- and
- computing the required die capacitance (CDIE) using IMAX.
Dependencies are inferred from the claim text.