Techniques for clock signal jitter generation
AssigneeMicron Technology, Inc.
InventorTyler J. Gomm
Life of this patent
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Abstract
A device may include an integrated circuit and a jitter generator located on the integrated circuit. The jitter generator may include a random number generator to generate a random number in response to a clock input signal. The jitter generator may also include delay-causing circuitry to receive the clock input signal, where the delay-causing circuitry may create a delayed clock input signal. The jitter generator may also include a phase mixer to receive the random number, the delayed clock input signal, and the clock input signal, where the phase mixer additionally outputs a clock output signal having the clock input signal and having jitter.
Claims20
A device, comprising:
- a random number generator configured to generate an on-signal and a mixing control signal;
- a first capacitor group characterized by a capacitance and comprising a first capacitor, wherein the first capacitor increases the capacitance by a first amount in response to the on-signal;
- and
- a phase mixer that receives a clock transmitted via the first capacitor group and generates a clock output based at least in part on the capacitance, wherein the clock output comprises jitter generated at least in part by the phase mixer adjusting the clock according to the mixing control signal.
A method, comprising:
- receiving a mode selection signal;
- varying a capacitance of a first capacitor using the mode selection signal;
- generating a plurality of signals in response to a current count of a random number generator changing in response to an input clock signal;
- generating a delayed input clock signal based at least in part on the input clock signal, the first capacitor, and variable delay circuitry operable in response to the mode selection signal;
- and
- generating a clock signal comprising jitter determined based at least in part on the plurality of signals, the input clock signal, and the delayed input clock signal.
Variable delay circuitry associated with a jitter generator, comprising:
- a first logic gate that receives a first clock signal;
- a second logic gate that receives a first control signal from a signal generator configured to generate the first control signal comprising a value indicative of an operational mode of the jitter generator;
- delay circuitry arranged to couple to the first logic gate and the second logic gate that permits propagation of the first clock signal adjusted via a first delay in response to the first control signal being received at the second logic gate;
- and
- a third logic gate arranged to couple to the first logic gate and the second logic gate, wherein the third logic gate and the second logic gate are selectively enabled or disabled at least partially in response to a second control signal.
Dependencies are inferred from the claim text.