Pseudo-non-volatile memory cells
AssigneeMicron Technology, Inc.
InventorsScott J. Derner, Christopher J. Kawamura
Life of this patent
Estimating the term…
Abstract
An example apparatus includes an array of memory cells coupled to an array power supply and a controller. The controller may be configured to cause a data value to be stored in at least one memory cell of the array of memory cells while the array of memory cells is operating in a first power state and a determination to be made that a change in a power status to a computing system coupled to the array of memory cells has occurred, wherein the change in the power status of the computing system is characterized by the computing device operating in a reduced power state. Responsive to the determination, the controller may be configured to cause the array power supply to be disabled to operate the array of memory cells in a second power state.
Claims29
An apparatus, comprising:
- an array of memory cells coupled to an array power supply and a controller, wherein the controller is configured to cause:
- a data value to be stored in at least one memory cell of the array of memory cells while the array of memory cells is operating in a first power state;
- a determination to be made that a change in a power status to a computing system coupled to the array of memory cells has occurred, wherein the change in the power status of the computing system is characterized by the computing device operating in a reduced power state;
- and
- responsive to the determination, cause the array power supply to be disabled to operate the array of memory cells in a second power state.
An apparatus, comprising:
- an array of memory cells comprising two transistor one capacitor (2T1C) memory cells;
- and
- a controller coupled to the array of memory cells, wherein the controller is configured to:
- provide a first amount of power to the array of memory cells when the array of memory cells are operating in a first power state;
- store data values in the 2T1C memory cells;
- provide a second amount of power to the array of memory cells to operate the array of memory cells in a second power state;
- and
- maintain the data values when the array of memory cells are operating in the second power state.
An apparatus, comprising:
- a first transistor having a first source/drain region coupled to a first plate of a capacitor and a second source/region coupled to a first bit line;
- a second transistor having a first source/drain region coupled to a second plate of the capacitor and a second source/drain region coupled to a second bit line;
- and
- a controller coupled to the first bit line and the second bit line, wherein the controller is configured to cause:
- a first voltage to be supplied to at least one of the first bit line, the second bit line, and a word line in a first mode of operation;
- a data value to be stored by the capacitor when the first voltage is supplied;
- a second voltage to be supplied to at least one of the first bit line, the second bit line, and the word line in a second mode of operation;
- and
- maintain the stored data value when the second voltage is supplied.
A method, comprising:
- initializing an array of memory cells comprising two transistor one capacitor (2T1C) memory cells by powering up a device coupleable to the array of memory cells up;
- operating the array of memory cells by providing a first amount of power to the array;
- receiving an indication from the device corresponding to a change in status of the device;
- responsive to receipt of the indication, disabling an array power supply to operate the array of memory cells using at least one of a second amount of power to the array or a third amount of power to the array while the device is receiving a reduced, non-zero amount of power.
Dependencies are inferred from the claim text.