Stack refresh control for memory device
AssigneeMicron Technology, Inc.
InventorYutaka Uemura
Life of this patent
Estimating the term…
Abstract
Apparatuses and methods for self-refreshing a plurality of dies are described. An example apparatus includes a first die including a first bank and a second bank, the first bank and the second bank including memory cells; and a second die vertically stacked with the first die, the second die including a third bank and a fourth bank, the third bank and the fourth bank including memory cells. The third bank is vertically aligned with the first bank. The first bank and the fourth bank are configured to be refreshed prior to refreshing the second bank and the fourth bank.
Claims21
An apparatus comprising:
- a first die comprising a plurality of first memory banks and a first power circuit;
- and
- a second die stacked on the first die, the second die comprising a plurality of second memory banks and a second power circuit;
- wherein the first die further comprises a first self-refresh circuit configured to perform a first self-refresh operation on a first memory bank among the plurality of first memory banks, wherein the first memory bank is closer to the first power circuit than to the second power circuit, wherein the first power circuit is not vertically aligned with the second power circuit;
- and
- wherein the second die further comprises a second self-refresh circuit configured to perform a second self-refresh operation on a second memory bank among the plurality of second memory banks.
An apparatus comprising:
- a first die comprising a plurality of first memory banks and a first layer ID circuit configured to provide layer ID information;
- and
- a second die comprising a plurality of second memory banks;
- wherein the first die further comprises a first self-refresh circuit configured to perform a first self-refresh operation on a first selected memory bank among the plurality of first memory banks, wherein the first self-refresh circuit is configured to generate a first self-refresh address of the first selected bank among the plurality of first memory banks based partly on the layer ID information and to generate a second self-refresh address of a second selected memory bank among the plurality of second memory banks based partly on the layer ID information.
An apparatus comprising:
- a plurality of first memory banks;
- a first self-refresh circuit configured to provide a plurality of first internal refresh addresses;
- and
- a first control circuit configured to perform first refresh operations on the plurality of first memory banks responsive, at least in part, to the plurality of first internal refresh addresses;
- wherein the first self-refresh circuit is further configured, responsive to first control information, to provide the plurality of first internal refresh addresses in a first order.
Dependencies are inferred from the claim text.