Ferroelectric memory cell with access line disturbance mitigation

A memory device, comprising:

• a ferroelectric memory cell coupled with a row line and a digit line;
• a sense circuit coupled with the digit line and configured to determine a first logic state of the ferroelectric memory cell by latching a first voltage or a second voltage for a read operation of the ferroelectric memory cell, wherein the sense circuit comprises a latch for latching the first voltage or the second voltage for the read operation, the latch comprising a first plurality of transistors having a first gate oxide thickness;
• and
• a write circuit coupled with the digit line and the sense circuit, wherein the write circuit comprises a driver for applying a third voltage or a fourth voltage to the digit line for the write back operation, the driver comprising a second plurality of transistors having a second gate oxide thickness, the write circuit configured to:
• write a second logic state to the ferroelectric memory cell based at least in part on the first voltage or the second voltage latched by the sense circuit, and
• write the second logic state by applying the third voltage or the fourth voltage to the digit line for a write back operation following the read operation, wherein at least one of the third voltage or the fourth voltage is different than the first voltage and the second voltage.

A method, comprising:

• reading a first logic state of a ferroelectric memory cell, the reading comprising coupling a sense circuit to a digit line associated with the ferroelectric memory cell and latching, at the sense circuit, a first voltage or a second voltage;
• decoupling the sense circuit from the digit line based at least in part on latching the first voltage or the second voltage;
• and
• writing a second logic state back to the ferroelectric memory cell, the writing comprising driving the digit line to a third voltage or a fourth voltage using a level shifter circuit for a write back operation following reading the first logic state, wherein at least one of the third voltage or the fourth voltage is different than the first voltage and the second voltage.

A method, comprising:

• reading a first logic state of a ferroelectric memory cell, the reading comprising coupling a sense circuit to a digit line associated with the ferroelectric memory cell and latching, at the sense circuit, a first voltage or a second voltage, wherein reading the first logic state comprises comparing a voltage generated on the digit line based at least in part on the ferroelectric memory cell with a reference voltage;
• decoupling the sense circuit from the digit line based at least in part on latching the first voltage or the second voltage;
• and
• writing a second logic state back to the ferroelectric memory cell, the writing comprising driving the digit line to a third voltage or a fourth voltage for a write back operation following reading the first logic state, wherein at least one of the third voltage or the fourth voltage is different than the first voltage and the second voltage.

A method, comprising:

• reading a first logic state of a ferroelectric memory cell, the reading comprising coupling a sense circuit to a digit line associated with the ferroelectric memory cell and latching, at the sense circuit, a first voltage or a second voltage;
• decoupling the sense circuit from the digit line based at least in part on latching the first voltage or the second voltage;
• writing a second logic state back to the ferroelectric memory cell, the writing comprising driving the digit line to a third voltage for a write back operation following reading the first logic state, wherein the third voltage is higher than the first voltage or the second voltage;
• and,
• controlling a first slew rate of the digit line when applying the third voltage.

A method, comprising:

• reading a first logic state of a ferroelectric memory cell, the reading comprising coupling a sense circuit to a digit line associated with the ferroelectric memory cell and latching, at the sense circuit, a first voltage or a second voltage;
• decoupling the sense circuit from the digit line based at least in part on latching the first voltage or the second voltage;
• coupling the sense circuit with a write circuit based at least in part on latching the first voltage or the second voltage;
• writing a second logic state to the ferroelectric memory cell, the writing comprising controlling a first slew rate of the digit line for driving the digit line to a third voltage that is higher than the first voltage or the second voltage and controlling, after driving the digit line to the third voltage, a second slew rate of the digit line for driving the digit line from the third voltage to a fourth voltage.