Access line management for an array of memory cells
AssigneeMicron Technology, Inc.
InventorDaniele Vimercati
Life of this patent
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Abstract
Methods, systems, and devices for access line management for an array of memory cells are described. Some memory devices may include a plate that is coupled with memory cells associated with a plurality of digit lines and/or a plurality of word lines. Because the plate is coupled with a plurality of digit lines and/or word lines, unintended cross-coupling between various components of the memory device may be significant. To mitigate the impact of unintended cross-coupling between various components, the memory device may float unselected word lines during one or more portions of an access operation. Accordingly, a voltage of each unselected word line may relate to the voltage of the plate as changes in plate voltage may occur.
Claims18
A method, comprising:
- driving a plate coupled with a first memory cell of an array of memory cells to a first voltage;
- identifying an access operation associated with a second memory cell of the array of memory cells;
- floating, for a duration, a first access line coupled with the first memory cell based at least in part on the access operation associated with the second memory cell, wherein the floating is based at least in part on applying a first control signal having a first voltage swing and a second control signal having a second voltage swing different than the first voltage swing to a driver for the first access line;
- and
- driving, during the duration, the plate from the first voltage to a second voltage based at least in part on the access operation associated with the second memory cell.
An apparatus, comprising:
- a memory cell coupled with an access line;
- a driver coupled with the access line;
- a control circuit coupled with the driver and operable to generate a first control signal for the driver and a second control signal for the driver, the second control signal having a different voltage swing than the first control signal;
- and
- a second control circuit coupled with the driver and operable to float a first node of the driver, wherein the driver is operable to float the access line based at least in part on the first node being floated.
An apparatus, comprising:
- a memory cell coupled with an access line;
- a driver coupled with the access line, wherein the driver is one of a subset of a set of drivers, each driver of the set coupled with a respective access line for a memory array that includes the memory cell;
- and
- a control circuit coupled with the driver and operable to generate a first control signal for the driver and a second control signal for the driver, the second control signal having a different voltage swing than the first control signal, wherein the control circuit is coupled with each driver of the subset and wherein the first control signal and the second control signal are common to the drivers of the subset.
An apparatus, comprising:
- a memory cell coupled with an access line;
- a driver coupled with the access line, wherein the driver comprises a first transistor in a cascode configuration with a second transistor;
- a control circuit coupled with the driver and operable to output a first control signal to the first transistor and a second control signal to a third transistor of the driver;
- and
- a second memory cell, wherein a source of the first transistor and a source of the third transistor are operable to be floated concurrent with an access operation for the second memory cell, and wherein the driver is operable to float the access line based at least in part on one or more of the source of the first transistor or the source of the third transistor being floated.
Dependencies are inferred from the claim text.