US 10,896,711 B2Granted

Memory device with memory cell structure including ferroelectric data storage layer, and a first gate and a second gate

AssigneeSamsung Electronics Co., Ltd.

InventorsKyung Hwan Lee, Seung Hyun Kim, Yong Seok Kim, Jun Hee Lim, Kohji Kanamori

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Abstract

A memory device includes memory cells, the memory cells each including a first gate, a second gate electrically isolated from the first gate, a first gate insulating layer including a data storage layer having a ferroelectric material and disposed between the first gate and a channel region, a second gate insulating layer disposed between the second gate and the channel region, a first switching cell connected between the memory cells and a source line, and a second switching cell connected between the memory cells and a bit line. The second switching cell includes a third gate, a fourth gate, a third gate insulating layer not including a data storage layer having the ferroelectric material and the third gate disposed between the third gate and the channel region, and a fourth gate insulating layer disposed between the fourth gate and the channel region.

Claims18

Dependent claims

A memory device comprising:

memory cells each including a first memory cell gate, a second memory cell gate electrically isolated from the first memory cell gate, a first gate insulating layer disposed between the first memory cell gate and a channel region, and a second gate insulating layer disposed between the second memory cell gate and the channel region, wherein the first memory cell gate and the second memory cell gate share the channel region, and the first gate insulating layer includes a data storage layer having a ferroelectric material;
a first switching cell including, a first switching cell gate and a second switching cell gate, and connected between the memory cells and a source line;
a second switching cell including a first switching cell gate and a second switching cell gate, and connected between the memory cells and a bit line;
for each memory cell, a channel separation layer adjacent to the channel region in a first direction, between the first memory cell gate and the second memory cell gate and having a width greater than a width of the channel region in a second direction different from the first direction;
and
a control circuit configured to control the memory cells, the first switching cell, and the second switching cell,
wherein the channel separation layer is formed of an insulating material.

4 more elements

A memory device comprising:

memory cells each including a first gate and a second gate separated from each other;
a first switching cell connected between the memory cells and a source line, the first switching cell including a first gate and a second gate;
a second switching cell connected between the memory cells and a bit line, the second switching cell including a first gate and a second gate;
a data storage layer having a ferroelectric material disposed between the first gates of the memory cells and a channel region and not disposed between the channel region and the first gate of at least one of the first switching cell and the second switching cell;
and
a control circuit configured to:
determine at least one selected memory cell and unselected memory cells among the memory cells, and
float the first gates of the unselected memory cells and the second gate of the at least one selected memory cell in a control operation with respect to the at least one selected memory cell,
wherein the control circuit is further configured to a pt, a program voltage to the first gate of the at least one selected memory cell and a pass voltage to the second gates of the unselected memory cells to boost the channel region of at least a portion of the memory cells, in a program operation of writing data to the at least one selected memory cell.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/522,121Filed 25 Jul 2019
Priority: KR 10-2018-016717121 Dec 2018
Published: US 2020/0202916 A125 Jun 2020
Granted: 19 Jan 2021
Term ends: Not estimatedThe source records don’t support an estimate.

Classification12 codes

G11C 11/223
Using ferroelectric elements: using MOS with ferroelectric gate insulating film
G11C 16/0483
Using variable threshold transistors, e.g. FAMOS: comprising cells having several storage transistors connected in series
G11C 11/22
Using electric elements: using ferroelectric elements
G11C 11/2253
Auxiliary circuits: address circuits or decoders