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US 10,896,709 B2Granted
Integrated circuit memory device and method of operating same
AssigneeSamsung Electronics Co., Ltd.
InventorArtur Antonyan
Life of this patent
Estimating the term…
Abstract
A memory device includes a memory cell array that includes memory cells, a row decoder that is connected with the memory cell array through word lines, a column decoder that is connected with the memory cell array through bit lines and source lines, and a write driver that outputs a write voltage in a write operation. The column decoder includes switches, which are respectively connected to the bit lines and are respectively connected to the source lines. During the write operation, a selected switch of the switches transfers the write voltage to a selected bit line of the bit lines. Each unselected switch of the switches electrically separates the write driver from a corresponding unselected bit line of the bit lines by using the write voltage.
Claims9
A memory device, comprising:
- an array of memory cells on an integrated circuit substrate;
- and
- a column decoder having a plurality of bidirectional switching circuits therein that are each electrically coupled by a plurality of pairs of bit lines to a corresponding plurality of columns of memory cells in said array of memory cells, said plurality of bidirectional switching circuits comprising a first bidirectional switching circuit having a first read/write decoder and a first plurality of switches therein, said first plurality of switches comprising a first switch having a first pair of terminals electrically coupled to a first of the plurality of pairs of bit lines and a second pair of terminals electrically coupled to the first read/write decoder, said first switch responsive to at least a first bit line access signal, which sets an enabled/disabled state within the first switch;
- wherein said first switch is configured to:
- (i) electrically couple the first of the plurality of pairs of bit lines together when the at least a first bit line access signal is in a first logic state, and (ii) electrically couple the first of the plurality of pairs of bit lines to the first read/write decoder when the at least a first bit line access signal is in a second logic state.
2 more elements
A memory device, comprising:
- an array of memory cells on an integrated circuit substrate;
- a column decoder having a plurality of bidirectional switching circuits therein that are each electrically coupled by a plurality of pairs of bit lines to a corresponding plurality of columns of memory cells in said array of memory cells, said plurality of bidirectional switching circuits comprising a first bidirectional switching circuit having a first read/write decoder and a first plurality of switches therein, said first plurality of switches comprising a first switch having a first pair of terminals electrically coupled to a first of the plurality of pairs of bit lines and a second pair of terminals electrically coupled to the first read/write decoder, said first switch responsive to at least a first bit line access signal, which sets an enabled/disabled state within the first switch;
- a first write driver electrically coupled to a write port of the first read/write decoder;
- and
- a first sense amplifier electrically coupled to a read port of the first read/write decoder.
2 more elements
A memory device, comprising:
- an array of memory cells on an integrated circuit substrate;
- and
- a column decoder having a plurality of bidirectional switching circuits therein that are each electrically coupled by a plurality of pairs of bit lines to a corresponding plurality of columns of memory cells in said array of memory cells, said plurality of bidirectional switching circuits comprising a first bidirectional switching circuit having a first read/write decoder and a first plurality of switches therein, said first plurality of switches comprising a first switch having a first pair of terminals electrically coupled to a first of the plurality of pairs of bit lines and a second pair of terminals electrically coupled to the first read/write decoder, said first switch responsive to at least a first bit line access signal, which sets an enabled/disabled state within the first switch;
- wherein said first switch is configured to:
- (i) electrically couple the first of the plurality of pairs of bit lines together and to a first reference voltage when the at least a first bit line access signal is in a first logic state, and (ii) electrically couple the first of the plurality of pairs of bit lines to the first read/write decoder when the at least a first bit line access signal is in a second logic state, opposite the first logic state;
- and
- wherein said first plurality of switches comprises a second switch having a first pair of terminals electrically coupled to a second of the plurality of pairs of bit lines and a second pair of terminals electrically coupled to the first read/write decoder and to the second pair of terminals associated with the first switch.
4 more elements
Dependencies are inferred from the claim text.