US 10,896,705 B2 · Feedback for multi-level signaling in a memory device

Abstract

Methods, systems, and devices for feedback for multi-level signaling in a memory device are described. The memory device may use pulse amplitude modulation (PAM) signaling (e.g., PAM4) that is synchronized with a clock signal using a double data rate (DDR) to communicate information with a host device. The memory device may include a first circuit for determining voltage levels of sampling events associated with a rising edge of the clock signal and a second circuit for determining voltage levels of sampling events associated with a falling edge of the clock signal. A feedback circuit may receive a feedback signal associated with the first circuit and modify the signal input into the second circuit. The feedback circuit may include a latch circuit configured to receive portions of the signal and receive a first control signal and a second control signal to tune portions of the signal.

Claims20

Dependent claims

An apparatus, comprising:

a receiver configured to decode a modulated signal of a sampling event, the receiver further comprising a first circuit and a second circuit, the first circuit configured to:
receive one or more symbols, each symbol represented by a voltage level;
generate a first feedback signal comprising information about a voltage level of a first preceding sampling event based at least in part on the one or more symbols;
receive a second feedback signal from the second circuit, the second feedback signal comprising information about a voltage level of a second preceding sampling event;
and
decode at least one of the one or more symbols based at least in part on the second feedback signal.

3 more elements

Dependencies are inferred from the claim text.

Feedback for multi-level signaling in a memory device

Life of this patent

Feedback for multi-level signaling in a memory device

Life of this patent

Abstract

Claims20