High-speed data readout apparatus and CMOS image sensor using the same

A data readout apparatus comprising:

• a counter array including an address decoder and a counter circuit, the address decoder being configured to receive an address, the counter circuit being coupled to the address decoder and perform, based on the address, a counting operation to convert an analog signal into data;
• a sense amplifier array coupled to the counter array to read out the data from the counter array;
• a precharge pulse generator to receive clock pulses and generate a precharge pulse signal;
• and
• a plurality of precharge drivers distributed over an area of the counter array and coupled in common to the precharge pulse generator, each precharge driver receiving the precharge pulse signal generated by the precharge pulse generator to reset differential data lines.

A data readout apparatus comprising:

• a counter array including an address decoder and a counter circuit, the address decoder being configured to receive an address, the counter circuit being coupled to the address decoder and perform, based on the address, a counting operation to convert an analog signal into data;
• a sense amplifier array coupled to the counter array to read out the data from the counter array;
• a clock driver arranged adjacent to the center of the counter array to distribute clock pulses;
• a first precharge pulse generator arranged adjacent to one side of the counter array and structured to receive the clock pulses from the clock driver and generate a precharge pulse signal;
• a second precharge pulse generator arranged adjacent to the other side of the counter array and structured to receive the clock pulses from the clock driver and generate the precharge pulse signal;
• and
• a plurality of precharge drivers distributed over an area of the counter array and coupled in common to the first and second precharge pulse generators receiving the precharge pulse signals generated by the first and second precharge pulse generators to reset differential data lines.

An image sensor comprising:

• a pixel array including imaging pixels for sensing incident light to output pixel signals corresponding to the incident light;
• a row decoder to select and control the imaging pixels within the pixel array at each row line;
• a data readout apparatus to read out the pixel signals outputted from the pixel array and output the read data;
• and
• a control circuit to control the operations of the row decoder and the data readout apparatus,
• wherein the data readout apparatus comprises:
• a counter array including an address decoder and a counter circuit, the address decoder being configured to receive a column address, the counter circuit being coupled to the address decoder and perform, based on the column address, a counting operation to convert the pixel signals into data;
• a sense amplifier array coupled to the counter array and structured to read out the data from the counter array;
• a clock driver arranged adjacent to the center of the counter array and structured to distribute a column clock;
• a first precharge circuit arranged at one side of the counter array and structured to receive the column clock from the clock driver and perform a precharge operation;
• and
• a second precharge circuit arranged at the other side of the counter array and structured to receive the column clock from the clock driver and perform the precharge operation.

An image sensor comprising:

• a pixel array including imaging pixels for sensing incident light to output pixel signals corresponding to the incident light;
• a row decoder to select and control the imaging pixels within the pixel array at each row line;
• a data readout apparatus to read out the pixel signals outputted from the pixel array and output the read data;
• and
• a control circuit to control the operations of the row decoder and the data readout apparatus,
• wherein the data readout apparatus comprises:
• a counter array including an address decoder and a counter circuit, the address decoder being configured to receive a column address, the counter circuit being coupled to the address decoder and perform, based on the column address, a counting operation to convert the pixel signals into data;
• a sense amplifier array coupled to the counter array and structured to read out the data from the counter array;
• a precharge pulse generator structured to receive a column clock and generate a precharge pulse signal;
• and
• a plurality of precharge drivers distributed over an area of the counter array and coupled in common to the precharge pulse generator, each precharge driver receiving the precharge pulse signal generated by the precharge pulse generator to reset differential data lines.

An image sensor comprising:

• a pixel array including imaging pixels for sensing incident light to output pixel signals corresponding to the incident light;
• a row decoder to select and control the imaging pixels within the pixel array at each row line;
• a data readout apparatus to read out the pixel signals outputted from the pixel array and output the read data;
• and
• a control circuit to control the operations of the row decoder and the data readout apparatus,
• wherein the data readout apparatus comprises:
• a counter array including an address decoder and a counter circuit, the address decoder being configured to receive a column address, the counter circuit being coupled to the address decoder and perform, based on the column address, a counting operation to convert the pixel signals into data;
• a sense amplifier array coupled to the counter array to read out the data from the counter array;
• a clock driver arranged adjacent to the center of the counter array to distribute a column clock;
• a first precharge pulse generator arranged at one side of the counter array and structured to receive the column clock from the clock driver and generate a precharge pulse signal;
• a second precharge pulse generator arranged at the other side of the counter array and structured to receive the column clock from the clock driver and generate the precharge pulse signal;
• and
• a plurality of precharge drivers distributed over an area of the counter array and coupled in common to the first and second precharge pulse generators receiving the precharge pulse signals generated by the first and second precharge pulse generators to reset differential data lines.