Netlist abstraction for circuit design floorplanning
AssigneeSynopsys, Inc.
InventorsBalkrishna R. Rashingkar, Leonardos J. van Bokhoven, Peiqing Zou
Life of this patent
Estimating the term…
Abstract
Systems and methods are described for creating a netlist abstraction that provides full-chip context for performing circuit design floorplanning. The netlist abstraction can include a top-level netlist abstraction that corresponds to the top-level portion of the netlist, and a physical block netlist abstraction for each physical block in the circuit design. Each physical block netlist abstraction can retain macros that are in the physical block.
Claims15
A method, comprising:
- receiving a plurality of block abstractions in a circuit abstraction, wherein a first block abstraction of the plurality of block abstractions includes a plurality of logical netlist abstractions and a macro with fixed pin locations, and wherein each logical netlist abstraction has an area that is substantially equal to a total area of cells abstracted by the logical netlist abstraction;
- receiving move bound information which specifies spatial boundaries within the first block abstraction where the plurality of logical netlist abstractions and the macro are permitted to be placed;
- and
- performing, by a processor, placement on the first block abstraction based on the move bound information and interconnectivity between the plurality of logical netlist abstractions and the macro.
A non-transitory computer-readable storage medium storing instructions, which when executed by a processor, cause the processor to:
- receive a plurality of block abstractions in a circuit abstraction, wherein a first block abstraction of the plurality of block abstractions included a plurality of logical netlist abstractions and a macro with fixed pin locations, and wherein each logical netlist abstraction has an area that is substantially equal to a total area of cells abstracted by the logical netlist abstraction;
- receive move bound information which specifies spatial boundaries within the first block abstraction where the plurality of logical netlist abstraction and the macro are permitted to be placed;
- and
- perform placement on the first block abstraction based on the move bound information and interconnectivity between the plurality of logical netlist abstractions and the macro.
An apparatus, comprising:
- a processor;
- and
- a non-transitory computer-readable storage medium storing instructions that, when executed by the processor, cause the processor to:
- receive a plurality of block abstractions in a circuit abstraction, wherein a first block abstraction of the plurality of block abstractions include a plurality of logical netlist abstractions and a macro with fixed pin locations and wherein each logical netlist abstraction has an area that is substantially equal to a total area of cells abstracted by the logical netlist abstraction;
- move bound information which specifies spatial boundaries within the first block abstraction where the plurality of logical netlist abstraction and the macro are permitted to be placed;
- and
- perform placement on the first block abstraction based on the move bound and interconnectivity between the plurality of logical netlist abstractions and the macro.
Dependencies are inferred from the claim text.