Verification apparatus and method for verifying operation of integrated circuit

A verification apparatus for verifying a logic operation of a target circuit including a circuit module configured to dynamically switch between synchronous transfer and asynchronous transfer of a data signal from a transmission side operable in accordance with a first clock signal to a reception side operable in accordance with a second clock signal that is synchronous or asynchronous with the first clock signal, the apparatus comprising a processor configured to:

• set a time window for detecting an erroneous change of a logical value of the data signal based on circuit data of the target circuit, wherein the time window ranges a first time period forward from an edge of the first clock signal and a second time period backward from the edge and excludes a sub range ranging a third time period forward from the edge and a fourth time period backward from the edge, the third time period shorter than the first time period, and the fourth time period shorter than the second time period;
• start a simulation of operation of the target circuit using the circuit data;
• during the simulation, determine whether or not the erroneous change of the logical value of the data signal is detected during the set time window;
• upon determining that the erroneous change is detected during the set time window, insert, into a test vector for the simulation, an erroneous sample that causes the reception side to fail in correctly receiving the data signal;
• and
• upon determining that the erroneous change is not detected during the set time window, continue the simulation without inserting the erroneous sample into the test vector.