Precise verification of a logic problem on a simulation accelerator
AssigneeInternational Business Machines Corporation
InventorsJohn A. Schumann, Debapriya Chatterjee, Bryant Cockcroft, Kevin Barnett, Piriya K. Hall, Paul Umbarger, Karen Yokum
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Abstract
A computer system includes a hardware accelerator and host processor. The hardware accelerator executes a simulation of a first logical model according to a plurality of simulation cycles. The host processor determines a fault checkpoint based on a logic fault that occurs in response to executing the simulation. The host processor verifies removal of the logic fault based on rerunning the simulation from the fault checkpoint.
Claims20
A computer system comprising:
- a hardware accelerator configured to execute a simulation of a first logical model according to a plurality of simulation cycles;
- and
- a host processor configured to determine a fault checkpoint based on a logic fault that occurs in response to executing the simulation,
- wherein the host processor verifies removal of the logic fault based on rerunning the simulation from the fault checkpoint.
A method of verifying a logic fault in an accelerator, the method comprising:
- executing, via the accelerator, a simulation of a first logical model according to a plurality of simulation cycles;
- determining, via a host processor, a fault checkpoint based on a logic fault that occurs in response to executing the simulation;
- and
- verifying, via the host processor, removal of the logic fault based on rerunning the simulation from the fault checkpoint.
A computer program product comprising a computer readable storage medium having program instructions embodied therewith the program instructions executable by a computer processor to cause the computer processor to perform a method of verifying a logic fault in an accelerator, the method comprising:
- executing, via the accelerator, a simulation of a first logical model according to a plurality of simulation cycles;
- determining, via a host processor, a fault checkpoint based on a logic fault that occurs in response to executing the simulation;
- and
- verifying, via the host processor, removal of the logic fault based on rerunning the simulation from the fault checkpoint.
Dependencies are inferred from the claim text.