High-level synthesis device, high-level synthesis method, and computer readable medium

A high-level synthesis method of a high-level synthesis device for executing high-level synthesis on a behavioral description describing a behavior of a circuit that implements a function, the behavioral description including a plurality of loop descriptions describing a repetitive process and a logical description describing a process that is not a repetitive process, the high-level synthesis method comprising:

• extracting loop descriptions that can be merged with the logical description without changing the function, as loop description candidates, from among the plurality of loop descriptions;
• calculating characteristics of the circuit of a case where the logical description is merged with each of the loop description candidates, as circuit characteristics;
• determining a loop description to be merged with the logical description, from the loop description candidates based on the circuit characteristics;
• and
• merging the logical description with the determined loop description.

A non-transitory computer readable medium storing a high-level synthesis program of a high-level synthesis device for executing high-level synthesis on a behavioral description describing a behavior of a circuit that implements a function, the behavioral description including a plurality of loop descriptions describing a repetitive process and a logical description describing a process which is not a repetitive process, the high-level synthesis program causing the high-level synthesis device which is a computer, to execute:

• an extraction process of extracting loop descriptions that can be merged with the logical description without changing the function, as loop description candidates, from among the plurality of loop descriptions;
• a circuit characteristics calculation process of calculating characteristics of the circuit of a case where the logical description is merged with each of the loop description candidates, as circuit characteristics;
• a determination process of determining a loop description to be merged with the logical description, from the loop description candidates based on the circuit characteristics;
• and
• a merging process of merging the logical description with the loop description determined by the determination process.