Gather-scatter cache architecture having plurality of tag and data banks and arbiter for single program multiple data (SPMD) processor
AssigneeIntel Corporation
InventorsJeffrey J. Cook, Jonathan D. Pearce, Srikanth T. Srinivasan, Rishiraj A. Bheda, David B. Sheffield, Abhijit Davare, Anton Alexandrovich Sorokin
Life of this patent
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Abstract
In one embodiment, a cache memory includes: a plurality of data banks, each of the plurality of data banks having a plurality of entries each to store a portion of a cache line distributed across the plurality of data banks; and a plurality of tag banks decoupled from the plurality of data banks, wherein a tag for a cache line is to be assigned to one of the plurality of tag banks. Other embodiments are described and claimed.
Claims20
An apparatus comprising:
- a cache memory having a fixed load-to-use latency pipeline, the cache memory comprising:
- a plurality of data banks, each of the plurality of data banks having a plurality of entries each to store a portion of a cache line distributed across the plurality of data banks;
- and
- a plurality of tag banks decoupled from the plurality of data banks, wherein a single tag for a cache line is to be assigned to one of the plurality of tag banks, and in response to a tag lookup hit and a data lookup hit for a request address from a first execution lane of a plurality of execution lanes, the cache memory is to send a first sub-cache line data block to at least some of the plurality of execution lanes.
A non-transitory machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:
- arbitrating, in a tag arbiter of a cache memory, between a plurality of execution lanes each providing a request address to the cache memory to select a first subset of the plurality of execution lanes, the arbitrating based on a tag bank index generated from the request address, and providing a tag portion of the request address of the first subset of the plurality of execution lanes to a tag bank of the cache memory;
- arbitrating, in a data arbiter of the cache memory, between the plurality of execution lanes to select a second subset of the plurality of execution lanes, the arbitrating based on a data bank index generated from the request address, and providing at least a data portion of the request address of the second subset of the plurality of execution lanes to a data bank of the cache memory;
- performing a lookup in a data bank of the cache memory for the second subset of execution lanes, and outputting a sub-cache line data block from the data bank, to at least a portion of the plurality of execution lanes, to enable at least one of the portion of execution lanes to consume the sub-cache line data block, wherein the at least one execution lane did not win the tag arbitrating or the data arbitrating.
A system comprising:
- a processor comprising:
- a plurality of execution lanes to perform parallel execution of instructions, each of the plurality of execution lanes including one or more execution circuits to perform operations on a sub-cache line data block;
- a cache memory coupled to the plurality of execution lanes, the cache memory comprising:
- a plurality of data banks, each of the plurality of data banks having a plurality of entries each to store a sub-cache line data block, wherein the plurality of data banks are collectively to store a cache line formed of the sub-cache line data block stored in the plurality of data banks;
- and
- a plurality of tag banks decoupled from the plurality of data banks, wherein a tag for the cache line is to be assigned to one of the plurality of tag banks, wherein in response to a tag lookup hit in a first tag bank and a data lookup hit in a first data bank in response to a request address from a first execution lane, the cache memory is to send a first sub-cache line data block to at least some of the plurality of execution lanes;
- and
- a system memory coupled to the processor.
Dependencies are inferred from the claim text.