Facilitating page table entry (PTE) maintenance in processor-based devices

A method for facilitating page table entry (PTE) maintenance, comprising:

• decoding, using a decode stage of an execution pipeline of a first processing element (PE) of a plurality of PEs of a processor-based device, a special page table entry (SP-PTE) field store instruction;
• executing the SP-PTE field store instruction to modify SP-PTE fields of a PTE of a page table in a system memory of the processor-based device, wherein the PTE is cached in a coherence granule corresponding to the PTE in a local cache of a first PE of the plurality of PEs;
• receive, via an interconnect bus by a second PE of the plurality of PEs, a bus request from the first PE for the coherence granule;
• and
• updating, by the second PE, a coherence state of a copy of the coherence granule in the local cache of the second PE to a coherence state of walker-readable (W) to indicate that the copy of the coherence granule can only be read by a hardware table walker (HTW) of the second PE.

A non-transitory computer-readable medium having stored thereon computer-executable instructions which, when executed by a processor, cause the processor to:

• decode a special page table entry (SP-PTE) field store instruction;
• execute the SP-PTE field store instruction to modify SP-PTE fields of a PTE of a page table in a system memory, wherein the PTE is cached in a coherence granule corresponding to the PTE in a local cache of a first PE of a plurality of PEs;
• receive, via an interconnect bus by a second PE of the plurality of PEs, a bus request from the first PE for the coherence granule;
• and
• update, by the second PE, a coherence state of a copy of the coherence granule in the local cache of the second PE to a coherence state of walker-readable (W) to indicate that the copy of the coherence granule can only be read by a hardware table walker (HTW) of the second PE.