Combinational address repair in memory controller

A memory controller that is a controller for a dynamic random-access memory, the memory controller comprising:

• a dedicated target address buffer for receiving a target address corresponding to a memory operation instruction;
• a first dedicated problem address buffer for holding a first problem address;
• a first dedicated repair address buffer for holding a first repair address to be used to replace the first problem address, wherein the first repair address is an address of a cache portion within the memory controller;
• a first address compare combinational circuit configured to compare the received target address held by the dedicated target address buffer with the first problem address held by the first dedicated repair address buffer and to generate a first match notification signal if the received target address and the first problem address match;
• a second dedicated problem address buffer for holding a second problem address;
• a second dedicated repair address buffer for holding a second repair address to be used to replace the second problem address;
• a second address compare combinational circuit configured to compare the received target address held by the dedicated target address buffer with the second problem address held by the second dedicated repair address buffer and to generate a second match notification signal if the received target address and the second problem address match;
• and
• an addressing combinational circuit configured to respond to the first match notification signal by causing the repair address within the first dedicated repair address buffer to be targeted by the memory operation instruction, and configured to respond to the second match notification signal by using the second repair address within the second dedicated repair address buffer to be targeted by the memory operation instruction.

A method for controlling memory, said memory comprising:

• receiving a target address corresponding to a memory operation instruction;
• holding a repair address to be used to replace a problem address, wherein the repair address is an address of a cache portion within a memory controller;
• comparing the received target address with the problem address;
• generating a match notification signal if the received target address and the problem address match;
• and
• responding to the match notification signal by causing the repair address to be targeted by the memory operation instruction.