Highly configurable memory architecture for partitioned global address space memory systems

A method for identifying from an address an appropriate target node and a location in that node that holds desired data related to that address, comprising the steps of:

• generating a logical address using a logical address generator associated with a logical address space, wherein said logical address is mapped, in a uniform partitioned global address space (PGAS) by application programs, into physical memory locations distributed across a multi-node parallel computer said logical address space is application independent and based on the property of each node;
• and
• receiving the logical address and using the logical address to retrieve a subspace index associated with one of a plurality of subspaces using a subspace configuration table to locate said desired data, each subspace is a set of a plurality of predefined addresses in the logical address space that does not overlap with another subspace, the subspace index provides access to configuration information associated with one of said subspaces that is used to access a lookup table that holds a description of translation functions needed for mapping between the logical address to a physical address of a memory element having different memory representations of an address space as well as to allow parts of the address space to be sharable amongst several programs at the same time, wherein different parts of the logical address are configured to have different properties and access rights depending on a physical target node, the subspace configuration table also uses the logical address to retrieve a physical node number associated with a memory partition, a node address associated with a processor in the multi-node parallel computer, and the access rights.

A system to identify from an address an appropriate target node from a plurality of nodes and a location in that node that holds desired data, comprising:

• a plurality of nodes, each node comprising:
• a memory that stores the desired data;
• a logical address generator that generates a logical address associated with a logical address space, wherein said logical address is mapped, in a uniform partitioned global address space (PGAS) by application programs, into physical memory locations in a multi-node parallel computer said logical address space is application independent and based on the property of each node;
• a subspace configuration table that receives a logical address and uses the logical address to retrieve a subspace index associated with one of a plurality of subspaces to locate desired data, wherein each subspace is a set of a plurality predefined addresses in the logical address space that does not overlap with another subspace, the subspace index provides access to configuration information associated with one of said subspaces that is used to access a lookup table that holds a description of translation functions needed for mapping between the logical address to a physical address of a memory element having different memory representations of an address space as well as to allow parts of the address space to be sharable amongst several programs at the same time, wherein different parts of the logical address are configured to have different properties and access rights depending on a physical target node, the subspace configuration table also uses the logical address to retrieve a physical node number associated with a memory partition, a node address associated with a processor in the multi-node parallel computer, and the access rights.

A method for identifying from an address an appropriate target node from a plurality of nodes and a location in that node that holds desired data, comprising the steps:

• providing a plurality of nodes, each node comprising:
• a memory for storing the desired data;
• generating a logical address using a logical address generator associated with a logical address space, wherein said logical address is mapped, in a uniform partitioned global address space (PGAS) by application programs, into physical memory locations in a multi-node parallel computer said logical address space is application independent and based on the property of each node;
• and
• receiving the logical address and using the logical address to retrieve a subspace index associated with one of a plurality of subspaces using a subspace configuration table to locate said desired data in said memory of said node, wherein each subspace is a set of a plurality of predefined addresses in the logical address space that does not overlap with another subspace, the subspace index provides access to configuration information associated with one of said subspaces that is used to access a lookup table that holds a description of translation functions needed for mapping between the logical address to a physical address of a memory element having different memory representations of an address space as well as to allow parts of the address space to be sharable amongst several programs at the same time, wherein different parts of the logical address are configured to have different properties and access rights depending on a physical target node, the subspace configuration table also uses the logical address to retrieve a physical node number associated with a memory partition, a node address associated with a processor in multi-node parallel computer, and the access rights.