Determine soft error resilience while verifying architectural compliance
AssigneeInternational Business Machines Corporation
InventorsOphir Erez, Bodo Hoppe, Divya K. Joshi, Gerrit Koch, Parminder Singh
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Abstract
Verifying architectural compliance of a processor core using processor-sparing functions. A simulation of a model for a register-transfer level design of the processor core is performed. A first state of the model is dumped, when no error exists. An error is injected in the model. A second state of the model is dumped, after the injected error is detected in the simulation. Upon dumping the second state, the model is reset and initialized with the first state. State information of the second state is loaded in the reset and initialized model.
Claims20
A computer program product for verifying architectural compliance of a processor core, the computer program product comprising:
- a computer readable storage medium readable by a processing circuit and storing instructions for performing a method comprising:
- performing a simulation of a model for a register-transfer level design of the processor core;
- during execution of the simulation, searching the model for an error;
- based on no error being detected during the searching, determining whether a dumping condition has been fulfilled;
- based on no error being detected during the searching and on determining that the dumping condition has been fulfilled, dumping a first state of said model;
- based on completing dumping the first state of the model, injecting an error in said model;
- based on injecting the error in the model, continuing with execution of the simulation until detecting the error in the simulation, and responsive to detecting the error in the simulation, performing processor-sparing by:
- dumping a second state of said model;
- responsive to dumping the second state, resetting and initializing said model with the first state;
- and
- responsive to resetting and initializing said model with the first state, loading state information of the second state in the reset and initialized model.
A computer system for verifying architectural compliance of a processor core, the computer system comprising:
- memory;
- and
- a processor in communication with the memory, wherein the computer system is configured to perform a method, said method comprising:
- performing a simulation of a model for a register-transfer level design of the processor core;
- during execution of the simulation, searching the model for an error;
- based on no error being detected during the searching, determining whether a dumping condition has been fulfilled;
- based on no error being detected during the searching and on determining that the dumping condition has been fulfilled, dumping a first state of said model;
- based on completing dumping the first state of the model, injecting an error in said model;
- based on injecting the error in the model, continuing with execution of the simulation until detecting the error in the simulation, and responsive to detecting the error in the simulation, performing processor-sparing by:
- dumping a second state of said model;
- responsive to dumping the second state, resetting and initializing said model with the first state;
- and
- responsive to resetting and initializing said model with the first state, loading state information of the second state in the reset and initialized model.
A computer-implemented method of verifying architectural compliance of a processor core, the computer-implemented method comprising:
- performing a simulation of a model for a register-transfer level design of the processor core;
- during execution of the simulation, searching the model for an error;
- based on no error being detected during the searching, determining whether a dumping condition has been fulfilled;
- based on no error being detected during the searching and on determining that the dumping condition has been fulfilled, dumping a first state of said model;
- based on completing dumping the first state of the model, injecting an error in said model;
- based on injecting the error in the model, continuing with execution of the simulation until detecting the error in the simulation, and responsive to detecting the error in the simulation, performing processor-sparing by:
- dumping a second state of said model;
- responsive to dumping the second state, resetting and initializing said model with the first state;
- and
- responsive to resetting and initializing said model with the first state, loading state information of the second state in the reset and initialized model.
Dependencies are inferred from the claim text.