Bus synchronization system that aggregates status
AssigneeTeradyne, Inc.
InventorsMichael C. Panis, Jeffrey S. Benagh, Richard Pye
Life of this patent
Estimating the term…
Abstract
An example test system includes instruments for controlling testing. Each instrument may be controlled by a processing unit. Each processing unit may be configured to operate on portions of a test program relevant to an instrument that the processing unit controls. A synchronization mechanism operates with at least some processing units to produce a synchronized sequence of actions, measurements, or measurements and actions at a test instrument interface absent intervention from a centralized controller.
Claims38
A system comprising:
- a computer bus;
- a host computer to execute test flows;
- and
- instrument modules, an instrument module comprising:
- resources;
- and
- a processing device;
- wherein resources operated on by a test flow define a domain;
- wherein the host computer is configured to output commands including a sync command in the test flow to the instrument modules, the sync command for causing the instrument module to provide a status to the computer bus and to pause the processing device;
- wherein statuses from the instrument modules in the domain are aggregated on the computer bus, and wherein information is distributed to the instrument modules based on the statuses aggregated;
- wherein the processing device is configured to resume executing commands based on the information;
- wherein the instrument module comprises an endpoint device to provide status to the computer bus;
- wherein the endpoint device comprises a contributing endpoint device;
- and
- wherein the contributing endpoint device is configured to receive the information from the computer bus and to generate a signal based on the information to trigger operation of one or more of the resources.
A system comprising:
- a computer bus;
- a host computer to execute test flows;
- and
- instrument modules, an instrument module comprising:
- resources;
- and
- a processing device;
- wherein resources operated on by a test flow define a domain;
- wherein the host computer is configured to output commands including a sync command in the test flow to the instrument modules, the sync command for causing the instrument module to provide a status to the computer bus and to pause the processing device;
- wherein statuses from the instrument modules in the domain are aggregated on the computer bus, and wherein information is distributed to the instrument modules based on the statuses aggregated;
- wherein the processing device is configured to resume executing commands based on the information;
- wherein the instrument module comprises an endpoint device;
- and
- wherein the endpoint device comprises a non-contributing endpoint device to receive the information from the computer bus and to generate a signal based on the information to trigger operation of one or more of the resources.
A system comprising:
- a computer bus;
- a host computer to execute test flows;
- and
- instrument modules, an instrument module comprising:
- resources;
- and
- a processing device;
- wherein resources operated on by a test flow define a domain;
- wherein the host computer is configured to output commands including a sync command in the test flow to the instrument modules, the sync command for causing the instrument module to provide a status to the computer bus and to pause the processing device;
- wherein statuses from the instrument modules in the domain are aggregated on the computer bus, and wherein information is distributed to the instrument modules based on the statuses aggregated;
- wherein the processing device is configured to resume executing commands based on the information;
- wherein the host computer is programmed to execute a test program that includes multiple, separate instruction flows, the multiple, separate instruction flows including the test flow;
- wherein the instrument module comprises an endpoint device;
- and
- wherein the endpoint device is configured to subscribe to one or more of the multiple, separate instruction flows.
A system comprising:
- a computer bus;
- a host computer to execute test flows;
- and
- instrument modules, an instrument module comprising:
- resources;
- and
- a processing device;
- wherein resources operated on by a test flow define a domain;
- wherein the host computer is configured to output commands including a sync command in the test flow to the instrument modules, the sync command for causing the instrument module to provide a status to the computer bus and to pause the processing device;
- wherein statuses from the instrument modules in the domain are aggregated on the computer bus, and wherein information is distributed to the instrument modules based on the statuses aggregated;
- wherein the processing device is configured to resume executing commands based on the information;
- and
- wherein the status comprises bits that are encoded in time-division-multiple-access fashion onto the computer bus using a periodic frame comprised of multiple bits.
A system comprising:
- a computer bus;
- a host computer to execute test flows;
- and
- instrument modules, an instrument module comprising:
- resources;
- and
- a processing device;
- wherein resources operated on by a test flow define a domain;
- wherein the host computer is configured to output commands including a sync command in the test flow to the instrument modules, the sync command for causing the instrument module to provide a status to the computer bus and to pause the processing device;
- wherein statuses from the instrument modules in the domain are aggregated on the computer bus, and wherein information is distributed to the instrument modules based on the statuses aggregated;
- wherein the processing device is configured to resume executing commands based on the information;
- and
- wherein at least some bits of the information represent a system time alignment signal to set system clock counters on the instrument modules to at least one of a specified value or a specified time that is in a payload on the computer bus.
A system comprising:
- a computer bus;
- instrument modules, an instrument module comprising:
- resources;
- and
- a processing device to execute commands from a queue;
- wherein the processing device is configured, in response to encountering at least one sync command in the queue, to cause the instrument module to provide a status to the computer bus and to pause the processing device;
- wherein statuses from the instrument modules are aggregated on the computer bus, and wherein information is distributed to the instrument modules based on the statuses aggregated;
- wherein the processing device is configured to resume executing commands based on the information;
- wherein the instrument module comprises an endpoint device to provide status to the computer bus;
- wherein the endpoint device comprises a contributing endpoint device;
- and
- wherein the contributing endpoint device is configured to receive the information from the computer bus and to generate a signal based on the information to trigger operation of one or more of the resources.
A test system comprising:
- instruments for controlling testing, each instrument being controlled by a processing unit, each processing unit being configured to operate on portions of a test program relevant to an instrument that the processing unit controls;
- and
- a synchronization mechanism operating with at least some processing units to produce a synchronized sequence of actions, measurements, or measurements and actions at a test instrument interface absent intervention from a centralized controller;
- wherein the synchronization mechanism is configured to:
- enable each processing unit to transmit status data in response to a synch command, the status data indicating whether the processing unit has completed a portion of the test program;
- receive and to aggregate status data across all processing units;
- and
- transmit one or more aggregated status bits back to all processing units;
- and
- wherein a processing unit among the at least some processing units is configured to resume execution based on the aggregated status bits.
A test system comprising:
- instruments for controlling testing, each instrument being controlled by a processing unit, each processing unit being configured to operate on portions of a test program relevant to an instrument that the processing unit controls;
- and
- a synchronization mechanism operating with at least some processing units to produce a synchronized sequence of actions, measurements, or measurements and actions at a test instrument interface absent intervention from a centralized controller;
- wherein the synchronization mechanism is configured to:
- enable each processing unit to transmit status data indicating whether the processing unit has completed a portion of the test program;
- receive and to aggregate status data across all processing units;
- and
- transmit one or more aggregated status bits back to all processing units;
- and
- wherein a processing unit is configured to perform operations comprising:
- when the processing unit has completed a portion of the test program, the processing unit indicates, on a synchronization bus, that the processing unit has completed the portion of the test program and, before proceeding to a next portion of the test program, the processing unit receives the one or more aggregated status bits indicating that all other processing units in the test system have completed portions of the test program.
A test system comprising:
- instruments for controlling testing, each instrument being controlled by a processing unit, each processing unit being configured to operate on portions of a test program relevant to an instrument that the processing unit controls;
- and
- a synchronization mechanism operating with at least some processing units to produce a synchronized sequence of actions, measurements, or measurements and actions at a test instrument interface absent intervention from a centralized controller;
- wherein the synchronization mechanism is configured to:
- enable each processing unit to transmit status data indicating whether the processing unit has completed a portion of the test program;
- receive and to aggregate status data across all processing units;
- and
- transmit one or more aggregated status bits back to all processing units;
- and
- wherein the synchronization mechanism has a defined timing relative to system clocks so that multiple instruments can receive the one or more aggregated status bits and be triggered to perform an action, a measurement, or both an action and a measurement with predictable and repeatable timing alignment among multiple instruments.
A test system comprising:
- instruments for controlling testing, each instrument being controlled by a processing unit, each processing unit being configured to operate on portions of a test program relevant to an instrument that the processing unit controls;
- and
- a synchronization mechanism operating with at least some processing units to produce a synchronized sequence of actions, measurements, or measurements and actions at a test instrument interface absent intervention from a centralized controller;
- wherein the synchronization mechanism is configured to:
- enable each processing unit to transmit status data indicating whether the processing unit has completed a portion of the test program;
- receive and to aggregate status data across all processing units;
- and
- transmit one or more aggregated status bits back to all processing units;
- and
- wherein the status data comprises one or more status bits that are encoded in time-division-multiple-access fashion onto a serial data bus using a periodic frame.
A test system comprising:
- instruments for controlling testing, each instrument being controlled by a processing unit, each processing unit being configured to operate on portions of a test program relevant to an instrument that the processing unit controls;
- and
- a synchronization mechanism operating with at least some processing units to produce a synchronized sequence of actions, measurements, or measurements and actions at a test instrument interface absent intervention from a centralized controller;
- wherein the synchronization mechanism is configured to:
- enable each processing unit to transmit status data indicating whether the processing unit has completed a portion of the test program;
- receive and to aggregate status data across all processing units;
- and
- transmit one or more aggregated status bits back to all processing units;
- and
- wherein at least some of the one or more aggregated status bits transmitted to the processing units represent a system time alignment signal to set system clock counters on the instruments to a specified value.
A system comprising:
- a computer bus;
- instrument modules, an instrument module comprising:
- resources;
- and
- a processing device to execute commands from a queue;
- wherein the processing device is configured, in response to encountering at least one sync command in the queue, to cause the instrument module to provide a status to the computer bus and to pause the processing device;
- wherein statuses from the instrument modules are aggregated on the computer bus, and wherein information is distributed to the instrument modules based on the statuses aggregated;
- wherein the processing device is configured to resume executing commands based on the information;
- wherein the instrument module comprises an endpoint device;
- and
- wherein the endpoint device comprises a non-contributing endpoint device to receive the information from the computer bus and to generate a signal based on the information to trigger operation of one or more of the resources.
A system comprising:
- a computer bus;
- instrument modules, an instrument module comprising:
- resources;
- and
- a processing device to execute commands from a queue;
- wherein the processing device is configured, in response to encountering at least one sync command in the queue, to cause the instrument module to provide a status to the computer bus and to pause the processing device;
- wherein statuses from the instrument modules are aggregated on the computer bus, and wherein information is distributed to the instrument modules based on the statuses aggregated;
- wherein the processing device is configured to resume executing commands based on the information;
- and
- wherein the status comprises bits that are encoded in time-division-multiple-access fashion onto the computer bus using a periodic frame comprised of multiple bits.
A system comprising:
- a computer bus;
- instrument modules, an instrument module comprising:
- resources;
- and
- a processing device to execute commands from a queue;
- wherein the processing device is configured, in response to encountering at least one sync command in the queue, to cause the instrument module to provide a status to the computer bus and to pause the processing device;
- wherein statuses from the instrument modules are aggregated on the computer bus, and wherein information is distributed to the instrument modules based on the statuses aggregated;
- wherein the processing device is configured to resume executing commands based on the information;
- and
- wherein at least some bits of the information represent a system time alignment signal to set system clock counters on the instrument modules to at least one of a specified value or a specified time that is in a payload on the computer bus.
Dependencies are inferred from the claim text.