Implementing SEU detection method and circuit

A design structure embodied in a machine readable medium used in a design process, the design structure comprising:

• a circuit tangibly embodied in the machine readable medium used in the design process, said circuit for implementing single event upset (SEU) parity detection, said a SEU parity detection circuit detecting unwanted state changes due to SEUs in a latch having a default state of zero;
• said SEU parity detection circuit comprising:
• the latch including an L1 latch and an L2 latch with the L2 latch having the connected output and being used and monitored for a flip due to SEU;
• a pair of series-connected field effect transistors (FETs) connected between a drive input of a parity control circuit and ground potential and having a respective gate input applied by the L1 latch and the L2 latch;
• and an L2 clock applied to the L2 latch and the parity control circuit;
• wherein the design structure, when read and used in the manufacture of a semiconductor chip produces a chip comprising said SEU parity detection circuit.

A method for implementing single event upset (SEU) parity detection comprising:

• providing a single event upset (SEU) parity detection circuit for detecting unwanted state changes due to SEUs in a latch having a default state of zero;
• providing the latch including an L1 latch and an L2 latch with the L2 latch having the connected output and being used and monitored for a flip due to SEU;
• providing a pair of series-connected field effect transistors (FETs) connected between a drive input of a parity control circuit and ground potential and having a respective gate input applied by the L1 latch and the L2 latch;
• applying an L2 clock to the L2 latch and the parity control circuit.