Low latency synchronization for operation cache and instruction cache fetching and decoding instructions

An instruction fetch and decode unit for converting instruction addresses of a first predicted address block into decoded micro-operations for output to an operations queue that stores decoded micro-operations in program order, and for subsequent execution by a remainder of an instruction execution pipeline, the instruction fetch and decode unit comprising:

• a shared fetch logic configured to:
• provide an index associated with the first predicted address block to an operation cache tag array to obtain a first tag associated with a first operation cache tag array entry and a second tag associated with a second operation cache tag array entry,
• in a first computer clock cycle, determine that both the first tag and the second tag match a tag derived from the predicted address block and that an end address associated with the first operation cache tag array entry matches a start address associated with the second operation cache tag array entry, and
• in the first computer clock cycle, identify a set of instructions for which decoded micro-operations are stored in an operation cache data array of an operation cache path, as instructions at addresses associated with both the first operation cache tag array entry and the second operation cache tag array entry;
• an operation cache queue configured to store a first operation cache queue entry for the set of instructions, the first operation cache queue entry including an indication indicating whether to wait to receive a signal from an instruction cache path to proceed;
• and
• an operation cache data read logic configured to obtain decoded micro-operations corresponding to the first operation cache queue entry from the operation cache, and to output the decoded micro-operations corresponding to the first operation cache queue entry to the operations queue, at a time that is based on the indication of the first operation cache queue entry indicating whether to wait to receive the signal from the instruction cache path to proceed.

A processor comprising:

• an instruction fetch and decode unit for converting instruction addresses of a first predicted address block into decoded micro-operations for output to an operations queue that stores decoded micro-operations in program order, and for subsequent execution by a remainder of an instruction execution pipeline;
• and
• the remainder of the instruction execution pipeline,
• wherein the instruction fetch and decode unit comprises:
• a shared fetch logic configured to:
• provide an index associated with the first predicted address block to an operation cache tag array to obtain a first tag associated with a first operation cache tag array entry and a second tag associated with a second operation cache tag array entry,
• in a first computer clock cycle, determine that both the first tag and the second tag match a tag derived from the predicted address block and that an end address associated with the first operation cache tag array entry matches a start address associated with the second operation cache tag array entry, and
• in the first computer clock cycle, identify a set of instructions for which decoded micro-operations are stored in an operation cache data array of an operation cache path, as instructions at addresses associated with both the first operation cache tag array entry and the second operation cache tag array entry;
• an operation cache queue configured to store a first operation cache queue entry for the set of instructions, the first operation cache queue entry including an indication indicating whether to wait to receive a signal from an instruction cache path to proceed;
• and
• an operation cache data read logic configured to obtain decoded micro-operations corresponding to the first operation cache queue entry from the operation cache, and to output the decoded micro-operations corresponding to the first operation cache queue entry to the operations queue, at a time that is based on the indication of the first operation cache queue entry indicating whether to wait to receive the signal from the instruction cache path to proceed.