Implementing a received add program counter immediate shift (ADDPCIS) instruction using a micro-coded or cracked sequence

A computer-implemented method for implementing a received add program counter immediate shift (ADDPCIS) instruction using a micro-coded or cracked sequence, comprising:

• recognizing register operand and integer terms associated with the ADDPCIS instruction;
• and
• setting a value of a target register associated with the ADDPCIS instruction in accordance with the integer term summed with another term by:
• obtaining a next instruction address (NIA),
• moving the NIA to a first temporary register of a register file and storing the NIA in the first temporary register,
• determining whether register files for function return addresses correspond to a general purpose register or do not correspond to the general purpose register,
• moving the NIA from the first temporary register to the general purpose register in an event the function return addresses correspond to the general purpose register,
• moving the NIA from the first temporary register to a second temporary register in an event the function return addresses do not correspond to the general purpose register, and
• adding a shifted immediate constant to a value stored in the second temporary register.