Storage controller, storage device including the same, and operation method of storage controller

A storage controller, comprising:

• a physical layer configured to communicate with an external device;
• an NVMe control unit connected with the physical layer through a system bus;
• and
• a clock managing unit,
• wherein the NVMe control unit includes:
• a control register block configured to receive information from the external device, based on a first clock;
• a command fetch block configured to fetch a command from the external device, based on a second clock;
• a direct memory access (DMA) engine configured to perform a DMA operation with the external device, based on a third clock;
• a completion block configured to write completion information to the external device, based on the fourth clock;
• and
• an interrupt block configured to transmit an interrupt signal to the external device, based on a fifth clock, and
• wherein the storage controller communicates with the external device, based on a nonvolatile memory express (NVMe) interface;
• and
• wherein the clock managing unit is configured to selectively activate and independently enable or selectively deactivate and independently disable each of the first clock, the second clock, the third clock, the fourth clock, and the fifth clock, depending on operations of the control register block, the command fetch block, the DMA engine, the completion block, and the interrupt block.

A storage device, comprising:

• a plurality of nonvolatile memory devices;
• and
• a storage controller configured to control the plurality of nonvolatile memory devices,
• wherein the storage controller includes:
• an NVMe control unit configured to perform operations including fetching a command from an external device, executing an operation corresponding to the fetched command, writing completion information about the operation to the external device, and transmitting an interrupt signal to the external device, based on a plurality of clocks;
• and
• a clock managing unit configured to selectively activate and independently enable or selectively deactivate and independently disable each of the plurality of clocks depending on operations of the NVMe control unit among the fetching, the executing, the writing, and the transmitting, and
• wherein the storage controller communicates with the external device, based on a nonvolatile memory express (NVMe) interface.